公开(公告)号：US20120115307A1

公开(公告)日：2012-05-10

申请号：US13253425

申请日：2011-10-05

申请人： Sang Wook Park ,  Tae Gyeong Chung ,  Ho Geon Song ,  Won Chul Lim

发明人： Sang Wook Park ,  Tae Gyeong Chung ,  Ho Geon Song ,  Won Chul Lim

IPC分类号： H01L21/78

CPC分类号： H01L21/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

摘要翻译： 制造半导体芯片的方法包括提供包括电路区域的半导体衬底，用激光束照射半导体衬底以形成易碎层，以及抛光半导体衬底以将半导体衬底的电路区域彼此分离为半导体芯片 。 在半导体衬底的抛光期间可以完全去除易碎层。

公开(公告)号：US08431442B2

公开(公告)日：2013-04-30

申请号：US13253425

申请日：2011-10-05

申请人： Sang Wook Park ,  Tae Gyeong Chung ,  Ho Geon Song ,  Won Chul Lim

发明人： Sang Wook Park ,  Tae Gyeong Chung ,  Ho Geon Song ,  Won Chul Lim

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing semiconductor chips includes providing a semiconductor substrate including circuit regions, irradiating the semiconductor substrate with a laser beam onto to form a frangible layer, and polishing the semiconductor substrate to separate the circuit regions of the semiconductor substrate from one another into semiconductor chips. The frangible layer may be removed completely during the polishing of the semiconductor substrate.

摘要翻译： 制造半导体芯片的方法包括提供包括电路区域的半导体衬底，用激光束照射半导体衬底以形成易碎层，以及抛光半导体衬底以将半导体衬底的电路区域彼此分离为半导体芯片 。 在半导体衬底的抛光期间可以完全去除易碎层。

公开(公告)号：US06340838B1

公开(公告)日：2002-01-22

申请号：US09241655

申请日：1999-02-02

申请人： Tae Gyeong Chung ,  Nam Seog Kim

发明人： Tae Gyeong Chung ,  Nam Seog Kim

IPC分类号： G01R3102

CPC分类号： H01R4/5066 ,  G01R1/0483 ,  H01L2224/73253 ,  H01R13/22

摘要： An apparatus for identifying a known good die according to an embodiment of the present invention includes a carrier for containing a bare semiconductor chip, a lid for covering the carrier, and a stopper for sealing the apparatus. The carrier includes: a body, in which a chip mount cavity and multiple vacuum suction holes are formed; inner connection terminals formed on a bottom surface of the chip mount cavity to communicate electrically with the bare chip; and outer connection terminals extending from the inner connection terminals to outside the body. The apparatus has an outer configuration of a conventional semiconductor package, so that the apparatus can fit into conventional test equipment. Therefore, the carrier can have a configuration of a plastic package, such as the SOP or SOJ, without a semiconductor chip. Accordingly, the apparatus according to the present invention can use conventional handling and burn-in test equipment in identifying of known good dies and thereby reduce production cost of the known good dies.

摘要翻译： 根据本发明的实施例的用于识别已知的良好裸片的装置包括用于容纳裸半导体芯片的载体，用于覆盖载体的盖和用于密封该装置的止动件。 载体包括：其中形成有芯片安装腔和多个真空吸孔的主体; 内部连接端子形成在芯片安装腔的底表面上以与裸芯片电气连通; 以及从内部连接端子延伸到主体外部的外部连接端子。 该装置具有常规半导体封装的外部结构，使得该装置可以装配到常规的测试设备中。 因此，载体可以具有没有半导体芯片的诸如SOP或SOJ的塑料封装的构造。 因此，根据本发明的装置可以使用常规的处理和老化测试设备来识别已知的良好模具，从而降低已知的良好模具的生产成本。

公开(公告)号：US5894107A

公开(公告)日：1999-04-13

申请号：US904756

申请日：1997-08-01

申请人： Kyu Jin Lee ,  Do Soo Jeong ,  Wan Gyan Choi ,  Tae Gyeong Chung

发明人： Kyu Jin Lee ,  Do Soo Jeong ,  Wan Gyan Choi ,  Tae Gyeong Chung

IPC分类号： H01L23/50 ,  H01L23/48 ,  H01L23/495 ,  H01L23/28

CPC分类号： H01L23/4951 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/30107

摘要： A method for manufacturing a chip-size package and the chip-size package produced by the method uses first and second lead frames which are prepared by a stamping process. The first lead frame has leads with receiving parts, and the leads are integrally formed with lengthwise side rails of the lead frame. The second lead frame has external connections which align with the receiving parts of the leads when the second lead frame is positioned on top of the first lead frame and attached thereto. Guide holes located on the crosswise side rails of both lead frames can be used to easily align the two lead frames. A semiconductor chip is then adhered to the underside of the first lead frame, and the bonding pads of the semiconductor chip are electrically connected to the leads of the first lead frame. Then the two lead frames and the chip are encapsulated, with only the external connections of the second lead frame remaining exposed to the outside. Solder balls are then attached to the external connections for mounting onto a substrate. This chip-size package is inexpensive to produce, because the first and second lead frames can be produced by a stamping process, which is less complex and cheaper than the conventional half-etching process.

摘要翻译： 制造芯片尺寸封装的方法和通过该方法制造的芯片尺寸封装使用通过冲压工艺制备的第一和第二引线框架。 第一引线框架具有带有接收部件的引线，并且引线与引线框架的纵向侧轨整体形成。 当第二引线框架位于第一引线框架的顶部并附接到其上时，第二引线框架具有与引线的接收部分对准的外部连接。 可以使用位于两个引线框架的横向侧轨上的导向孔来容易地对准两个引线框架。 然后将半导体芯片粘附到第一引线框架的下侧，并且半导体芯片的焊盘电连接到第一引线框架的引线。 然后，两个引线框架和芯片被封装，只有第二引线框架的外部连接保持暴露于外部。 然后将焊球连接到外部连接以安装到基板上。 这种芯片尺寸的封装是便宜的，因为第一和第二引线框架可以通过冲压工艺生产，该冲压工艺比传统的半蚀刻工艺不那么复杂和便宜。

公开(公告)号：US5660318A

公开(公告)日：1997-08-26

申请号：US509232

申请日：1995-07-31

申请人： Il Gyu Jung ,  Tae Gyeong Chung ,  Tae Koo Lee

发明人： Il Gyu Jung ,  Tae Gyeong Chung ,  Tae Koo Lee

IPC分类号： H01L21/60 ,  B23K20/02 ,  H01L21/603 ,  H01L21/58

CPC分类号： H01L24/80 ,  B23K20/023 ,  B23K2201/38 ,  H01L2224/16225 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14

摘要： An inner lead bonding apparatus having a heat dissipation plate attached to inner leads and to a support for upholding a lead frame of a tape automated bonding package. The heat dissipation plate is, during performance of an inner lead bonding process, located near the bonding interface of bumps formed on a semiconductor chip or on the inner leads and the inner leads, and includes a fastener for fixing itself to the support and elliptical bolt holes for enabling its contact position to the inner leads to be controllable.

摘要翻译： 一种内引线接合装置，其具有附接到内引线的散热板和用于支撑带自动接合封装的引线框的支撑。 在内引线接合工艺执行期间，散热板位于形成在半导体芯片或内引线和内引线上的凸点的接合界面附近，并且包括用于将自身固定到支撑件和椭圆螺栓 使得其与内部引线的接触位置能够被控制的孔。