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    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE
    1.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20120122286A1

    公开(公告)日：2012-05-17

    申请号：US13290285

    申请日：2011-11-07

    申请人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Do-Hyoung Kim ,  Dong-Woon Park

    发明人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Do-Hyoung Kim ,  Dong-Woon Park

    IPC分类号： H01L21/336 ,  H01L21/768

    CPC分类号： H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

    摘要翻译： 在制造半导体器件的方法中，依次在基板上的金属栅极结构和覆盖金属栅极结构的侧壁的第一绝缘夹层上形成第一蚀刻掩模和第二蚀刻掩模。 通过除去与第一蚀刻掩模或第二蚀刻掩模不重叠的第一绝缘夹层的一部分，形成开口以暴露基板的顶表面。 在衬底的暴露的顶表面上形成金属硅化物图案。 形成金属硅化物图案上的塞子以填充开口的剩余部分。 此外，可以使用平坦化层作为第二蚀刻掩模。

    Methods of manufacturing semiconductor device
    2.
    发明授权
    Methods of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08691693B2

    公开(公告)日：2014-04-08

    申请号：US13290285

    申请日：2011-11-07

    申请人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Do-Hyoung Kim ,  Dong-Woon Park

    发明人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Do-Hyoung Kim ,  Dong-Woon Park

    IPC分类号： H01L21/44 ,  H01L29/40

    CPC分类号： H01L21/76895 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： In a method of manufacturing a semiconductor device, a first etching mask and a second etching mask are formed sequentially on a metal gate structure on a substrate and a first insulating interlayer covering a sidewall of the metal gate structure respectively. An opening is formed to expose a top surface of the substrate by removing a portion of the first insulating interlayer not overlapped with the first etching mask or the second etching mask. A metal silicide pattern is formed on the exposed top surface of the substrate. A plug on the metal silicide pattern is formed to fill a remaining portion of the opening. Further, a planarization layer may be used as the second etching mask.

    摘要翻译： 在制造半导体器件的方法中，依次在基板上的金属栅极结构和覆盖金属栅极结构的侧壁的第一绝缘夹层上形成第一蚀刻掩模和第二蚀刻掩模。 通过除去与第一蚀刻掩模或第二蚀刻掩模不重叠的第一绝缘夹层的一部分，形成开口以暴露基板的顶表面。 在衬底的暴露的顶表面上形成金属硅化物图案。 形成金属硅化物图案上的塞子以填充开口的剩余部分。 此外，可以使用平坦化层作为第二蚀刻掩模。

    Method of manufacturing a semiconductor device
    3.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08563383B2

    公开(公告)日：2013-10-22

    申请号：US13252621

    申请日：2011-10-04

    申请人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

    发明人： Sang-Jin Kim ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

    摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

    摘要翻译： 制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案 栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如 蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
    4.
    发明申请
    METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20120122284A1

    公开(公告)日：2012-05-17

    申请号：US13252621

    申请日：2011-10-04

    申请人： Sang-Jin KIM ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

    发明人： Sang-Jin KIM ,  Jong-Chan Shin ,  Yong-Kug Bae ,  Myeong-Cheol Kim ,  Do-Hyoung Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823425 ,  H01L21/823437 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7834

    摘要： A method of manufacturing a semiconductor device includes forming a plurality of gate structures including a metal on a substrate having an isolation layer, forming first insulating interlayer patterns covering sidewalls of the gate structures, forming first capping layer patterns and a second capping layer pattern on the gate structures and the first insulating interlayer patterns, the first capping layer patterns covering upper faces of the gate structures, and the second capping layer pattern overlapping the isolation layer, partially removing the first insulating interlayer patterns using the first and the second capping layer patterns as etching masks to form first openings that expose portions of the substrate, forming metal silicide patterns on the portions of the substrate exposed in the forming of the first openings, and forming conductive structures on the metal silicide patterns.

    摘要翻译： 制造半导体器件的方法包括在具有隔离层的衬底上形成包括金属的多个栅极结构，形成覆盖栅极结构的侧壁的第一绝缘层间图案，形成第一覆盖层图案和第二覆盖层图案 栅极结构和第一绝缘层间图案，第一覆盖层图案覆盖栅极结构的上表面，第二覆盖层图案与隔离层重叠，使用第一和第二覆盖层图案部分地去除第一绝缘层间图案，如 蚀刻掩模以形成暴露基板部分的第一开口，在形成第一开口的裸露部分上形成金属硅化物图案，并在金属硅化物图案上形成导电结构。

    Phase change memory device and method of fabricating the same
    7.
    发明授权
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07767568B2

    公开(公告)日：2010-08-03

    申请号：US11905244

    申请日：2007-09-28

    申请人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    发明人： Hyeong-Geun An ,  Hideki Horii ,  Jong-Chan Shin ,  Dong-Ho Ahn ,  Jun-Soo Bae ,  Jeong-Hee Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L27/2463 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1683

    摘要： A phase change memory device and method of manufacturing the same is provided. A first electrode having a first surface is provided on a substrate. A second electrode having a second surface at a different level from the first surface is on the substrate. The second electrode may be spaced apart from the first electrode. A third electrode may be formed corresponding to the first electrode. A fourth electrode may be formed corresponding to the second electrode. A first phase change pattern may be interposed between the first surface and the third electrode. A second phase change pattern may be interposed between the second surface and the fourth electrode. Upper surfaces of the first and second phase change patterns may be on the same plane.

    摘要翻译： 提供了一种相变存储器件及其制造方法。 具有第一表面的第一电极设置在基板上。 具有与第一表面不同的第二表面的第二电极在基板上。 第二电极可以与第一电极间隔开。 可以对应于第一电极形成第三电极。 可以对应于第二电极形成第四电极。 可以在第一表面和第三电极之间插入第一相变图案。 可以在第二表面和第四电极之间插入第二相变图案。 第一和第二相变图案的上表面可以在同一平面上。

    Method for fabricating an integrated circuit device
    9.
    发明授权
    Method for fabricating an integrated circuit device 有权
    集成电路器件的制造方法

    公开(公告)号：US06316358B1

    公开(公告)日：2001-11-13

    申请号：US09346271

    申请日：1999-07-01

    申请人： Jong-Chan Shin

    发明人： Jong-Chan Shin

    IPC分类号： H01L2144

    CPC分类号： H01L21/76838 ,  H01L21/32139

    摘要： A method for forming a uniform conductive pattern on an integrated circuit substrate having a step by a single photography process. An exposure mask has a different pattern in accordance with the topology of the integrated circuit substrate. The exposure mask has a increased inter-pattern space at a lower portion of the step and has a reduced inter-pattern space at a upper portion of the step. During the exposure process, a sufficient amount of light is applied to a photoresist layer at the lower portion of the step and an optical amount of light is applied to the photoresist layer at the upper portion of the step. As a result, scum phenomenon at the lower portion of the step can be prevented. Further, overetching of the conductive pattern at the upper portion of the step can be prevented.

    摘要翻译： 在具有通过单次摄影处理的步骤的集成电路基板上形成均匀导电图案的方法。 曝光掩模根据集成电路基板的拓扑结构具有不同的图案。 曝光掩模在台阶的下部具有增加的图案间空间，并且在台阶的上部具有减小的图案间空间。 在曝光过程中，在步骤的下部向光致抗蚀剂层施加足够量的光，并且在步骤的上部将光量施加到光致抗蚀剂层。 结果，可以防止在台阶下部的浮渣现象。 此外，可以防止在台阶的上部处的导电图案的过蚀刻。

    Phase-changeable memory device and method of manufacturing the same
    10.
    发明授权
    Phase-changeable memory device and method of manufacturing the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US07563639B2

    公开(公告)日：2009-07-21

    申请号：US11733131

    申请日：2007-04-09

    申请人： Hee-Ju Shin ,  Jong-Chan Shin ,  Soon-Oh Park ,  Hyeong-Geun An ,  Han-Bong Ko

    发明人： Hee-Ju Shin ,  Jong-Chan Shin ,  Soon-Oh Park ,  Hyeong-Geun An ,  Han-Bong Ko

    IPC分类号： H01L21/06

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

    摘要： In a semiconductor memory device and a method of manufacturing the same, an insulating layer is formed on a substrate having a logic region on which a first pad is provided and a cell region on which a second pad and a lower electrode are subsequently provided. The insulating layer is etched to be a first insulating layer pattern having a first opening exposing the first pad. A first plug is formed in the first opening. The first insulating layer pattern where the first plug is formed is etched to be a second insulating layer pattern having a second opening exposing the lower electrode. A second plug including a phase-changeable material is formed in the second opening. A conductive wire and an upper electrode are formed on the first plug and the second plug, respectively.

    摘要翻译： 在半导体存储器件及其制造方法中，在具有设置有第一焊盘的逻辑区域的衬底上形成绝缘层，并且随后设置有第二焊盘和下电极的单元区域。 绝缘层被蚀刻成具有第一开口的第一绝缘层图案，该第一开口露出第一焊盘。 第一插头形成在第一开口中。 将形成有第一插塞的第一绝缘层图案蚀刻成具有暴露下电极的第二开口的第二绝缘层图案。 包括相变材料的第二插头形成在第二开口中。 导线和上电极分别形成在第一插头和第二插头上。