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    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20130065369A1

    公开(公告)日：2013-03-14

    申请号：US13671948

    申请日：2012-11-08

    申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

    发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

    摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US20120083077A1

    公开(公告)日：2012-04-05

    申请号：US13228433

    申请日：2011-09-08

    申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

    发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

    IPC分类号： H01L21/336 ,  H01L21/28

    CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

    摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

    Three dimensional semiconductor memory device and method of fabricating the same
    3.
    发明授权
    Three dimensional semiconductor memory device and method of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08309405B2

    公开(公告)日：2012-11-13

    申请号：US13228433

    申请日：2011-09-08

    申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

    发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Jung-Ho Kim ,  Ji-Hoon Choi

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/44

    CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

    摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

    Three dimensional semiconductor memory device and method of fabricating the same
    4.
    发明授权
    Three dimensional semiconductor memory device and method of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08815676B2

    公开(公告)日：2014-08-26

    申请号：US13671948

    申请日：2012-11-08

    申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

    发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

    摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
    6.
    发明申请
    METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20120115293A1

    公开(公告)日：2012-05-10

    申请号：US13287509

    申请日：2011-11-02

    申请人： Jin-Tae NOH ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

    发明人： Jin-Tae NOH ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  B82Y40/00

    CPC分类号： H01L27/1157 ,  H01L27/10855 ,  H01L27/11582

    摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

    摘要翻译： 在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。 绝缘夹层包括与牺牲层的材料不同的材料。 通过绝缘夹层和牺牲层形成至少一个开口。 至少一个开口露出基板。 种子层使用第一硅源气体形成在至少一个开口的内壁上。 通过种植种子层在至少一个开口中形成多晶硅沟道。 去除牺牲层以在绝缘夹层之间形成多个凹槽。 在槽中分别形成有多个栅极结构。

    Gate of a transistor and method of forming the same
    7.
    发明申请
    Gate of a transistor and method of forming the same 审中-公开
    晶体管的栅极及其形成方法

    公开(公告)号：US20110045667A1

    公开(公告)日：2011-02-24

    申请号：US12926151

    申请日：2010-10-28

    申请人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sang-Ryol Yang

    发明人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sang-Ryol Yang

    IPC分类号： H01L21/28

    CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385

    摘要： A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.

    摘要翻译： 晶体管的栅极包括形成在半导体器件上的栅极氧化层，包含掺杂有硼的多晶硅并形成在栅极氧化物层上的第一导电层图案，包括通过化学气相沉积工艺形成的非晶硅的扩散防止层图案，其使用 形成在第一导电层图案上的具有丙硅烷（Si 3 H 8）的反应气体和形成在扩散防止层图案上的包含金属硅化物的第二导电层图案。 由于PMOS晶体管的栅极包括具有优异表面形态的扩散防止层，因此充分防止了杂质的扩散。 因此，可以降低PMOS晶体管的阈值电压，并且可以提高阈值电压分布。

    Methods of manufacturing semiconductor devices
    8.
    发明授权
    Methods of manufacturing semiconductor devices 有权
    制造半导体器件的方法

    公开(公告)号：US08445367B2

    公开(公告)日：2013-05-21

    申请号：US13287509

    申请日：2011-11-02

    申请人： Jin-Tae Noh ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

    发明人： Jin-Tae Noh ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang ,  Jin-Gyun Kim ,  Sang-Ryol Yang

    IPC分类号： H01L21/20 ,  H01L21/36

    CPC分类号： H01L27/1157 ,  H01L27/10855 ,  H01L27/11582

    摘要： In a method of manufacturing a semiconductor device, a plurality of sacrificial layers and a plurality of insulating interlayers are repeatedly and alternately on a substrate. The insulating interlayers include a different material from a material of the sacrificial layers. At least one opening through the insulating interlayers and the sacrificial layers are formed. The at least one opening exposes the substrate. The seed layer is formed on an inner wall of the at least one opening using a first silicon source gas. A polysilicon channel is formed in the at least one opening by growing the seed layer. The sacrificial layers are removed to form a plurality of grooves between the insulating interlayers. A plurality of gate structures is formed in the grooves, respectively.

    摘要翻译： 在制造半导体器件的方法中，多个牺牲层和多个绝缘中间层在衬底上重复交替。 绝缘夹层包括与牺牲层的材料不同的材料。 通过绝缘夹层和牺牲层形成至少一个开口。 至少一个开口露出基板。 种子层使用第一硅源气体形成在至少一个开口的内壁上。 通过种植种子层在至少一个开口中形成多晶硅沟道。 去除牺牲层以在绝缘夹层之间形成多个凹槽。 在槽中分别形成有多个栅极结构。

    Gate of a transistor and method of forming the same
    10.
    发明申请
    Gate of a transistor and method of forming the same 审中-公开
    晶体管的栅极及其形成方法

    公开(公告)号：US20080048277A1

    公开(公告)日：2008-02-28

    申请号：US11892223

    申请日：2007-08-21

    申请人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sang-Ryol Yang

    发明人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sang-Ryol Yang

    IPC分类号： H01L29/40 ,  H01L21/3205

    CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385

    摘要： A gate of a transistor includes a gate oxide layer formed on a semiconductor device, a first conductive layer pattern including polysilicon doped with boron and formed on the gate oxide layer, a diffusion preventing layer pattern including amorphous silicon formed by a chemical vapor deposition process using a reaction gas having trisilane (Si3H8) and formed on the first conductive layer pattern, and a second conductive layer pattern including metal silicide and formed on the diffusion preventing layer pattern. Since a gate of PMOS transistor includes a diffusion preventing layer having an excellent surface morphology, diffusion of impurities is sufficiently prevented. Thus, the threshold voltage of PMOS transistor may be reduced and threshold voltage distribution may be improved.

    摘要翻译： 晶体管的栅极包括形成在半导体器件上的栅极氧化层，包含掺杂有硼的多晶硅并形成在栅极氧化物层上的第一导电层图案，包括通过化学气相沉积工艺形成的非晶硅的扩散防止层图案，其使用 形成在第一导电层图案上的具有丙硅烷（Si 3 N 8 H 8）的反应气体和形成在扩散防止层上的金属硅化物的第二导电层图案 模式。 由于PMOS晶体管的栅极包括具有优异表面形态的扩散防止层，因此充分防止了杂质的扩散。 因此，可以降低PMOS晶体管的阈值电压，并且可以提高阈值电压分布。