利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

34 条记录 (耗时 0.02 秒)

    Method of manufacturing a non-volatile memory device having a vertical structure
    1.
    发明授权
    Method of manufacturing a non-volatile memory device having a vertical structure 有权
    制造具有垂直结构的非易失性存储器件的方法

    公开(公告)号：US08927366B2

    公开(公告)日：2015-01-06

    申请号：US13610344

    申请日：2012-09-11

    申请人： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

    发明人： Sung-hae Lee ,  Ki-hyun Hwang ,  Jin-gyun Kim

    IPC分类号： H01L21/04 ,  H01L27/115

    CPC分类号： H01L27/11556 ,  H01L27/11582

    摘要： A method of manufacturing a non-volatile memory device, wherein the method includes: alternately stacking interlayer sacrificial layers and interlayer insulating layers on a substrate; forming a plurality of first openings that pass through the interlayer sacrificial layers and the interlayer insulating layers to expose a first portion of the substrate; forming a semiconductor region on a side wall and a lower surface of each of the first openings; forming an embedded insulating layer in each of the first openings; forming a first conductive layer on the embedded insulating layer inside each of the first openings; forming a second opening exposing a second portion of the substrate and forming an impurity region on the second portion; forming a metal layer to cover the first conductive layer and the impurity region; and forming the metal layer into a metal silicide layer.

    摘要翻译： 一种制造非易失性存储器件的方法，其中所述方法包括：在衬底上交替层叠层间牺牲层和层间绝缘层; 形成穿过所述层间牺牲层和所述层间绝缘层的多个第一开口，以露出所述衬底的第一部分; 在每个所述第一开口的侧壁和下表面上形成半导体区域; 在每个所述第一开口中形成嵌入绝缘层; 在每个所述第一开口内的所述嵌入式绝缘层上形成第一导电层; 形成露出所述衬底的第二部分并在所述第二部分上形成杂质区的第二开口; 形成覆盖所述第一导电层和所述杂质区域的金属层; 以及将所述金属层形成为金属硅化物层。

    NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    NONVOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 失效
    非易失性存储器件及其制造方法

    公开(公告)号：US20100187595A1

    公开(公告)日：2010-07-29

    申请号：US12694655

    申请日：2010-01-27

    申请人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    发明人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    IPC分类号： H01L29/788 ,  H01L21/8247

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

    摘要： Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

    摘要翻译： 提供了非易失性存储器件及其制造方法。 非易失性存储器件包括衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的栅极间电介质层结构以及栅极间电介质层结构上的控制栅极。 栅极间电介质层结构包括第一氧化硅层，第一氧化硅层上的高电介质层和与第一氧化硅层相对的高电介质层上的第二氧化硅层。高电介质层可以包括第一氧化硅层 和第二高介电层彼此层叠，并且第一高介电层可以具有比第二高介电层更低的电子陷阱位置密度，并且可以具有比第二高介电层更大的能带隙或导带偏移 。

    NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM
    3.
    发明申请
    NON-VOLATILE MEMORY DEVICE, MEMORY CARD AND SYSTEM 审中-公开
    非易失性存储器件，存储卡和系统

    公开(公告)号：US20090321810A1

    公开(公告)日：2009-12-31

    申请号：US12476574

    申请日：2009-06-02

    申请人： Min-Kyung RYU ,  Byong-sun JU ,  Myoung-bum LEE ,  Seung-hyun LIM ,  Sung-hae LEE ,  Young-sun KIM

    发明人： Min-Kyung RYU ,  Byong-sun JU ,  Myoung-bum LEE ,  Seung-hyun LIM ,  Sung-hae LEE ,  Young-sun KIM

    IPC分类号： H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/513

    摘要： Provided is a non-volatile memory device including; a substrate having source/drain regions and a channel region between the source/drain regions; a tunneling insulating layer formed in the channel region of the substrate; a charge storage layer formed on the tunneling insulating layer; a blocking insulating layer formed on the charge storage layer, and comprising a silicon oxide layer and a high-k dielectric layer sequentially formed; and a control gate formed on the blocking insulating layer, wherein an equivalent oxide thickness of the silicon oxide layer is equal to or greater than that of the high-k dielectric layer.

    摘要翻译： 提供了一种非易失性存储器件，包括： 具有源极/漏极区域和源极/漏极区域之间的沟道区域的衬底; 形成在所述基板的沟道区域中的隧道绝缘层; 形成在隧道绝缘层上的电荷存储层; 形成在所述电荷存储层上的阻挡绝缘层，并且依次形成氧化硅层和高k电介质层; 以及形成在所述阻挡绝缘层上的控制栅极，其中所述氧化硅层的等效氧化物厚度等于或大于所述高k电介质层的氧化物厚度。

    Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System
    5.
    发明申请
    Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System 有权
    包括立方体或四边形系统的绝缘层的半导体器件

    公开(公告)号：US20090085160A1

    公开(公告)日：2009-04-02

    申请号：US12238822

    申请日：2008-09-26

    申请人： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

    发明人： Jong-cheol Lee ,  Jun-noh Lee ,  Ki-vin Im ,  Ki-yeon Park ,  Sung-hae Lee ,  Sang-yeol Kang

    IPC分类号： H01L29/92

    CPC分类号： H01L29/51 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/513

    摘要： Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode.

    摘要翻译： 本发明提供一种半导体器件，其具有立方晶系或四方晶系的绝缘层，具有良好的电特性。 半导体器件包括：半导体衬底，包括有源区，形成在半导体衬底的有源区中的晶体管，形成在半导体衬底上的层间绝缘层和形成在层间绝缘层中的接触插塞;以及 其电连接到晶体管。 半导体器件可以包括形成在层间绝缘层上并且与电性连接的接触插塞的下电极，形成在下电极上的上电极和立方体系的绝缘层或包括 金属硅酸盐层。 绝缘层可以形成在下电极和上电极之间。

    Gate structure and related non-volatile memory device and method
    6.
    发明申请
    Gate structure and related non-volatile memory device and method 审中-公开
    门结构及相关非易失性存储器件及方法

    公开(公告)号：US20070007583A1

    公开(公告)日：2007-01-11

    申请号：US11474429

    申请日：2006-06-26

    申请人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Jin-Tae Noh

    发明人： Sung-Hae Lee ,  Ju-Wan Lim ,  Jae-Young Ahn ,  Jin-Tae Noh

    IPC分类号： H01L29/792

    CPC分类号： H01L29/792 ,  H01L29/40117

    摘要： A gate structure adapted for use in a SONOS device unit cell is disclosed. The gate structure comprises a charge trap insulator and a single electrode. The charge trap insulator comprises a multilayer structure comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. The single electrode is formed on the charge trap insulator, comprises a P-type impurity receptive semiconductor material, and is doped with P-type impurities.

    摘要翻译： 公开了一种适用于SONOS设备单元的门结构。 栅极结构包括电荷阱绝缘体和单个电极。 电荷陷阱绝缘体包括包含第一氧化硅层，氮化硅层和第二氧化硅层的多层结构。 单电极形成在电荷陷阱绝缘子上，包含P型杂质受体半导体材料，并掺杂有P型杂质。

    VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
    7.
    发明申请
    VERTICAL TYPE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    垂直型半导体器件及其制造方法

    公开(公告)号：US20140054675A1

    公开(公告)日：2014-02-27

    申请号：US13945336

    申请日：2013-07-18

    申请人： Chae-Ho Kim ,  Sung-Hae Lee ,  Toshiro Nakanishi ,  Dong-Woo Kim

    发明人： Sung-Hae LEE ,  Toshiro NAKANISHI ,  Dong-Woo KIM ,  Chae-Ho KIM

    IPC分类号： H01L29/792 ,  H01L29/66

    CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/66833

    摘要： According to example embodiments, a vertical type semiconductor device includes a pillar structure on a substrate. The pillar structure includes a semiconductor pattern and a channel pattern. The semiconductor pattern includes an impurity region. A first word line structure faces the channel pattern and is horizontally extended while surrounding the pillar structure. A second word line structure has one side facing the impurity region of the semiconductor pattern and another side facing the substrate. A common source line is provided at a substrate portion adjacent to a sidewall end portion of the second word line structure.

    摘要翻译： 根据示例性实施例，垂直型半导体器件包括在衬底上的柱结构。 柱结构包括半导体图案和沟道图案。 半导体图案包括杂质区域。 第一字线结构面向通道图案，并且在围绕柱结构的同时水平延伸。 第二字线结构具有面向半导体图案的杂质区域和面向衬底的另一侧的一侧。 在与第二字线结构的侧壁端部相邻的衬底部分处提供公共源极线。

    Nonvolatile memory devices and methods of manufacturing the same
    8.
    发明授权
    Nonvolatile memory devices and methods of manufacturing the same 失效
    非易失存储器件及其制造方法

    公开(公告)号：US08264026B2

    公开(公告)日：2012-09-11

    申请号：US12694655

    申请日：2010-01-27

    申请人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    发明人： Sung-Hae Lee ,  Byong-Sun Ju ,  Suk-Jin Chung ,  Young-Sun Kim

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

    摘要： Nonvolatile memory devices and related methods of manufacturing the same are provided. A nonvolatile memory device includes a tunneling layer on a substrate, a floating gate on the tunneling layer, an inter-gate dielectric layer structure on the floating gate, and a control gate on the inter-gate dielectric layer structure. The inter-gate dielectric layer structure includes a first silicon oxide layer, a high dielectric layer on the first silicon oxide layer, and a second silicon oxide layer on the high dielectric layer opposite to the first silicon oxide layer The high dielectric layer may include first and second high dielectric layers laminated on each other, and the first high dielectric layer may have a lower density of electron trap sites than the second high dielectric layer and may have a larger energy band gap or conduction band-offset than the second high dielectric layer.

    摘要翻译： 提供了非易失性存储器件及其制造方法。 非易失性存储器件包括衬底上的隧道层，隧道层上的浮动栅极，浮置栅极上的栅极间电介质层结构以及栅极间电介质层结构上的控制栅极。 栅极间电介质层结构包括第一氧化硅层，第一氧化硅层上的高电介质层和与第一氧化硅层相对的高电介质层上的第二氧化硅层。高电介质层可以包括第一氧化硅层 和第二高介电层彼此层叠，并且第一高介电层可以具有比第二高介电层更低的电子陷阱位置密度，并且可以具有比第二高介电层更大的能带隙或导带偏移 。

    Non-volatile semiconductor memory devices and methods of fabricating the same
    10.
    发明申请
    Non-volatile semiconductor memory devices and methods of fabricating the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20070063265A1

    公开(公告)日：2007-03-22

    申请号：US11601505

    申请日：2006-11-17

    申请人： Sung-Hae Lee ,  Chang-Hyun Lee ,  Ki-Hyun Hwang ,  Sung-Kweon Baek ,  Kwang-Min Park

    发明人： Sung-Hae Lee ,  Chang-Hyun Lee ,  Ki-Hyun Hwang ,  Sung-Kweon Baek ,  Kwang-Min Park

    IPC分类号： H01L29/788

    CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/513

    摘要： Nonvolatile memory devices and related methods of fabricating nonvolatile memory devices are disclosed. A nonvolatile memory device includes a tunnel insulation film on a semiconductor substrate, a charge-trapping layer on the tunnel insulation film, a block insulation film on the charge-trapping layer, and a gate electrode on the blocking insulation film. The blocking insulation film includes a stacked film structure of a high-dielectric film and a barrier insulation film. The high-dielectric film has a first potential barrier relative to the charge-trapping layer. The barrier insulation film has a second potential barrier relative to the charge-trapping layer which is higher than the first potential barrier. The blocking insulation film has a thickness in a range of about 5 Å to about 15 Å.

    摘要翻译： 公开了非易失性存储器件和制造非易失性存储器件的相关方法。 非易失性存储器件包括半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷俘获层，电荷俘获层上的块绝缘膜和阻挡绝缘膜上的栅电极。 阻挡绝缘膜包括高电介质膜和阻挡绝缘膜的叠层膜结构。 高电介质膜相对于电荷俘获层具有第一势垒。 阻挡绝缘膜相对于高于第一势垒的电荷俘获层具有第二势垒。 阻挡绝缘膜的厚度在约5至约15的范围内。