公开(公告)号：US06380579B1

公开(公告)日：2002-04-30

申请号：US09547940

申请日：2000-04-11

申请人： Sang-don Nam ,  Jin-won Kim

发明人： Sang-don Nam ,  Jin-won Kim

IPC分类号： H01L27108

CPC分类号： H01L28/75 ,  H01L28/55

摘要： A capacitor of a semiconductor device which uses a high dielectric layer and a method of manufacturing the same are provided. The capacitor includes a storage electrode having at least two conductive patterns which overlap each other and a thermally-stable material layer pattern being positioned between the conductive layer patterns. The storage electrode and the thermally-stable material layer pattern are formed by alternately forming a conductive layer and a thermally-stable material layer, and patterning the conductive layer and the thermally-stable material layer to have predetermined shapes. With the present structure, it is possible to prevent the storage electrode from being transformed or broken during a thermal treatment process for forming a high dielectric layer on the storage electrode or in a subsequent high temperature thermal treatment process.

摘要翻译： 提供了使用高介电层的半导体器件的电容器及其制造方法。 电容器包括具有彼此重叠的至少两个导电图案的存储电极和位于导电层图案之间的热稳定材料层图案。 存储电极和热稳定材料层图案通过交替形成导电层和热稳定材料层而形成，并且将导电层和热稳定材料层图案化以具有预定形状。 利用本结构，可以防止在用于在存储电极上形成高电介质层的热处理工艺中或在随后的高温热处理工艺中存储电极变形或破裂。

公开(公告)号：US20060024950A1

公开(公告)日：2006-02-02

申请号：US11084505

申请日：2005-03-18

申请人： Suk-Hun Choi ,  Byeong-ok Cho ,  Yoon-ho Son ,  Sang-don Nam

发明人： Suk-Hun Choi ,  Byeong-ok Cho ,  Yoon-ho Son ,  Sang-don Nam

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

公开(公告)号：US20050094452A1

公开(公告)日：2005-05-05

申请号：US10721480

申请日：2004-11-26

申请人： Kyu-Mann Lee ,  Kun-sang Park ,  Sang-don Nam

发明人： Kyu-Mann Lee ,  Kun-sang Park ,  Sang-don Nam

IPC分类号： G11C7/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L28/55 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76846 ,  H01L21/7687 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

摘要： A ferroelectric memory device includes an interlayer dielectric layer and a a protection adhesion layer formed thereon. A buried contact extends through the protection adhesion layer and the interlayer dielectric layer. A lower electrode is on a portion of the protection adhesion layer that is adjacent to the buried contact and on the buried contact. A ferroelectric layer covers the lower electrode and the protection adhesion layer. An upper electrode overlaps the lower electrode and covers the ferroelectric layer. Related methods are also disclosed.

摘要翻译： 铁电存储器件包括层间绝缘层和形成在其上的保护粘合层。 掩埋触点延伸穿过保护粘合层和层间介电层。 下电极位于保护粘合层的与埋入触点相邻并且与埋入触点相邻的部分上。 铁电层覆盖下电极和保护粘合层。 上电极与下电极重叠并覆盖铁电体层。 还公开了相关方法。

公开(公告)号：US06500763B2

公开(公告)日：2002-12-31

申请号：US09735901

申请日：2000-12-14

申请人： Jin-won Kim ,  Sang-don Nam ,  Wan-don Kim ,  Kab-jin Nam

发明人： Jin-won Kim ,  Sang-don Nam ,  Wan-don Kim ,  Kab-jin Nam

IPC分类号： H01L21302

CPC分类号： H01L28/91 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31122

摘要： A method for manufacturing an electrode of a capacitor used in a semiconductor device, wherein a support insulating layer, an etch stop layer including a tantalum oxide layer, and a mold sacrificial insulating layer are sequentially formed on a semiconductor substrate. The mold sacrificial insulating layer, the etch stop layer and the support insulating layer are sequentially patterned to form a three-dimensional mold for a storage node. A storage node layer is formed to cover the inner surface of the mold. Next, storage nodes for capacitors are formed by dividing the storage node layer. The residual mold sacrificial insulating layer is removed by selectively wet etching, using the tantalum oxide layer as an etch stopper.

摘要翻译： 在半导体器件中制造用于电容器的电极的方法，其中在半导体衬底上依次形成支撑绝缘层，包括氧化钽层的蚀刻停止层和模具牺牲绝缘层。 模具牺牲绝缘层，蚀刻停止层和支撑绝缘层被顺序地图案化以形成用于存储节点的三维模具。 形成存储节点层以覆盖模具的内表面。 接下来，通过划分存储节点层来形成用于电容器的存储节点。 通过使用氧化钽层作为蚀刻停止器，通过选择性湿法蚀刻除去残余模具牺牲绝缘层。

公开(公告)号：US07622379B2

公开(公告)日：2009-11-24

申请号：US11084505

申请日：2005-03-18

申请人： Suk-Hun Choi ,  Byeong-ok Cho ,  Yoon-ho Son ,  Sang-don Nam

发明人： Suk-Hun Choi ,  Byeong-ok Cho ,  Yoon-ho Son ,  Sang-don Nam

IPC分类号： H01L21/4763

CPC分类号： H01L21/76877 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/16

摘要： Methods of forming a metal contact structure include forming an interlayer insulating layer on a substrate, etching the interlayer insulating layer to form a hole, depositing a metal layer on the surface of the interlayer insulating layer including inside the hole, planarizing the metal layer to provide a buried portion of the metal layer in the hole and to remove portions of the metal layer outside of the hole, etching-back the buried portion of the metal layer in the hole such that some of the portion of the metal layer within the hole remains and depositing a conductive layer on the surface of the interlayer insulating layer and the portion of the metal layer that remains within the hole. Methods of forming a phase change memory device are also provided.

摘要翻译： 形成金属接触结构的方法包括在基板上形成层间绝缘层，蚀刻层间绝缘层以形成孔，在包括孔内部的层间绝缘层的表面上沉积金属层，平坦化金属层以提供 在孔中的金属层的掩埋部分并且去除孔的外部的金属层的部分，蚀刻孔中的金属层的掩埋部分，使得孔内的金属层的一些部分保持 以及在所述层间绝缘层的表面和所述金属层中保留在所述孔内的部分的表面上沉积导电层。 还提供了形成相变存储器件的方法。

公开(公告)号：US20050185486A9

公开(公告)日：2005-08-25

申请号：US10721480

申请日：2003-11-25

申请人： Kyu-Mann Lee ,  Kun-sang Park ,  Sang-don Nam

发明人： Kyu-Mann Lee ,  Kun-sang Park ,  Sang-don Nam

IPC分类号： G11C7/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

CPC分类号： H01L28/55 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76838 ,  H01L21/76846 ,  H01L21/7687 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

摘要： A ferroelectric memory device includes an interlayer dielectric layer and a a protection adhesion layer formed thereon. A buried contact extends through the protection adhesion layer and the interlayer dielectric layer. A lower electrode is on a portion of the protection adhesion layer that is adjacent to the buried contact and on the buried contact. A ferroelectric layer covers the lower electrode and the protection adhesion layer. An upper electrode overlaps the lower electrode and covers the ferroelectric layer. Related methods are also disclosed.

公开(公告)号：US06248640B1

公开(公告)日：2001-06-19

申请号：US09344585

申请日：1999-06-25

申请人： Sang-don Nam

发明人： Sang-don Nam

IPC分类号： H01L2120

CPC分类号： H01L28/56 ,  H01L21/28518 ,  H01L21/3165 ,  H01L28/60

摘要： A method of forming a capacitor of a semiconductor device which can prevent disconnection between lower electrodes by blanket-depositing a second conductive film for silicidation on a semiconductor substrate and forming an oxide of the second conductive film such as titanium dioxide (TiO2) on an interlayer dielectric using high temperature oxidation, before depositing a dielectric film, and which can obtain a high capacitance by forming both a silicide layer including the second conductive film, and the oxide of the second conductive film such as titanium dioxide (TiO2) having a high dielectric constant, on a lower electrode, and using the silicide layer and oxide as the dielectric film.

摘要翻译： 一种形成半导体器件的电容器的方法，其可以通过在半导体衬底上涂覆用于硅化的第二导电膜并在中间层上形成诸如二氧化钛（TiO 2）的第二导电膜的氧化物来防止下部电极之间的断开 在沉积电介质膜之前使用高温氧化的电介质，并且可以通过形成包括第二导电膜的硅化物层和第二导电膜的氧化物（例如具有高电介质的二氧化钛（TiO 2））来获得高电容 在下电极上，并且使用硅化物层和氧化物作为电介质膜。