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    Method of forming a high quality gate oxide at low temperatures
    5.
    发明授权
    Method of forming a high quality gate oxide at low temperatures 失效
    在低温下形成高质量栅极氧化物的方法

    公开(公告)号：US06551947B1

    公开(公告)日：2003-04-22

    申请号：US10164919

    申请日：2002-06-04

    申请人： Yoshi Ono ,  Jong-Jan Lee

    发明人： Yoshi Ono ,  Jong-Jan Lee

    IPC分类号： H01L2131

    CPC分类号： H01L21/3165

    摘要： A method of low-temperature oxidation of a silicon substrate includes placing a silicon wafer in a vacuum chamber; maintaining the silicon wafer at a temperature of between about room temperature and 350° C.; introducing an oxidation gas in the vacuum chamber including introducing an oxidation gas taken from the group of oxidation gases consisting of O2 and O3; dissociating the oxidation gas into radical oxygen with a xenon laser generating light at a wavelength of about 172 nm and flowing the radical oxygen over the silicon wafer; and forming an oxide layer on at least a portion of the silicon wafer.

    摘要翻译： 硅衬底的低温氧化的方法包括将硅晶片放置在真空室中; 将硅晶片保持在约室温至350℃之间的温度; 在真空室中引入氧化气体，包括引入从由O 2和O 3组成的氧化气体组取得的氧化气体; 用氙激光将氧化气体分解成自由基氧，产生波长为约172nm的光并使自由基氧流过硅晶片; 以及在所述硅晶片的至少一部分上形成氧化物层。

    Annealing of high-k dielectric materials
    6.
    发明授权
    Annealing of high-k dielectric materials 有权
    高k电介质材料的退火

    公开(公告)号：US06544906B2

    公开(公告)日：2003-04-08

    申请号：US10011219

    申请日：2001-10-25

    申请人： Antonio L. P. Rotondaro ,  Mark R. Visokay ,  Luigi Colombo

    发明人： Antonio L. P. Rotondaro ,  Mark R. Visokay ,  Luigi Colombo

    IPC分类号： H01L21469

    CPC分类号： H01L21/02323 ,  H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3165 ,  H01L21/318 ,  H01L29/517 ,  H01L29/518

    摘要： A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650° C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600° C. while the gate dielectric layer is in the ambient.

    摘要翻译： 用于退火高介电常数（高k）栅介质层的方法包括将包括一个或多个部分形成的晶体管的晶片放置在环境中。 环境可以包括氢气和氧化气体，或者环境可以包括一氧化二氮。 每个晶体管包括耦合到衬底的高k栅介质层。 该方法还包括在栅介质层处于环境中时将高k栅介质层加热到大于650℃的温度。 环境防止或减少在高k栅极电介质层和衬底之间的较低介电常数（低k）材料的形成。 用于退火高k栅介质层的另一种方法包括使用包括化学活性氧气的环境。 当使用这样的环境时，高k栅极电介质层被加热到不高于600℃的温度，同时栅介质层处于环境中。

    Annealing of high-K dielectric materials
    7.
    发明申请
    Annealing of high-K dielectric materials 有权
    高K电介质材料的退火

    公开(公告)号：US20020081826A1

    公开(公告)日：2002-06-27

    申请号：US10011219

    申请日：2001-10-25

    发明人： Antonio L. P. Rotondaro ,  Mark R. Visokay ,  Luigi Colombo

    IPC分类号： H01L021/4763 ,  H01L021/3205

    CPC分类号： H01L21/02323 ,  H01L21/02148 ,  H01L21/02156 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/02194 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/3165 ,  H01L21/318 ,  H01L29/517 ,  H01L29/518

    摘要： A method for annealing a high dielectric constant (high-k) gate dielectric layer includes placing a wafer including one or more partially formed transistors in an ambient. The ambient may include hydrogen and an oxidizing gas or the ambient may include nitrous oxide. Each transistor includes a high-k gate dielectric layer coupled to a substrate. The method further includes heating the high-k gate dielectric layer to a temperature greater than 650null C. while the gate dielectric layer is in the ambient. The ambient prevents or reduces the formation of lower dielectric constant (lower-k) material between the high-k gate dielectric layer and the substrate. Another method for annealing a high-k gate dielectric layer includes the use of an ambient including chemically active oxygen gas. When such an ambient is used, the high-k gate dielectric layer is heated to a temperature not greater than 600null C. while the gate dielectric layer is in the ambient.

    摘要翻译： 用于退火高介电常数（高k）栅介质层的方法包括将包括一个或多个部分形成的晶体管的晶片放置在环境中。 环境可以包括氢气和氧化气体，或者环境可以包括一氧化二氮。 每个晶体管包括耦合到衬底的高k栅介质层。 该方法还包括在栅介质层处于环境中时将高k栅介质层加热到大于650℃的温度。 环境防止或减少在高k栅极电介质层和衬底之间的较低介电常数（低k）材料的形成。 用于退火高k栅介质层的另一种方法包括使用包括化学活性氧气的环境。 当使用这样的环境时，高k栅极电介质层被加热到不高于600℃的温度，同时栅介质层处于环境中。

    Method for forming capacitor of semiconductor device using high temperature oxidation
    8.
    发明授权
    Method for forming capacitor of semiconductor device using high temperature oxidation 有权
    使用高温氧化形成半导体器件的电容器的方法

    公开(公告)号：US06248640B1

    公开(公告)日：2001-06-19

    申请号：US09344585

    申请日：1999-06-25

    申请人： Sang-don Nam

    发明人： Sang-don Nam

    IPC分类号： H01L2120

    CPC分类号： H01L28/56 ,  H01L21/28518 ,  H01L21/3165 ,  H01L28/60

    摘要： A method of forming a capacitor of a semiconductor device which can prevent disconnection between lower electrodes by blanket-depositing a second conductive film for silicidation on a semiconductor substrate and forming an oxide of the second conductive film such as titanium dioxide (TiO2) on an interlayer dielectric using high temperature oxidation, before depositing a dielectric film, and which can obtain a high capacitance by forming both a silicide layer including the second conductive film, and the oxide of the second conductive film such as titanium dioxide (TiO2) having a high dielectric constant, on a lower electrode, and using the silicide layer and oxide as the dielectric film.

    摘要翻译： 一种形成半导体器件的电容器的方法，其可以通过在半导体衬底上涂覆用于硅化的第二导电膜并在中间层上形成诸如二氧化钛（TiO 2）的第二导电膜的氧化物来防止下部电极之间的断开 在沉积电介质膜之前使用高温氧化的电介质，并且可以通过形成包括第二导电膜的硅化物层和第二导电膜的氧化物（例如具有高电介质的二氧化钛（TiO 2））来获得高电容 在下电极上，并且使用硅化物层和氧化物作为电介质膜。

    Printed dopant layers
    9.
    发明授权
    Printed dopant layers 有权
    印刷掺杂剂层

    公开(公告)号：US08304780B2

    公开(公告)日：2012-11-06

    申请号：US12797274

    申请日：2010-06-09

    申请人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    发明人： Arvind Kamath ,  James Montague Cleeves ,  Joerg Rockenberger ,  Patrick Smith ,  Fabio Zürcher

    IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112

    CPC分类号： H01L21/316 ,  H01L21/02211 ,  H01L21/02288 ,  H01L21/02318 ,  H01L21/3165 ,  H01L27/1285 ,  H01L27/1292 ,  H01L29/66757 ,  H01L29/78621

    摘要： A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

    摘要翻译： 一种用于制造诸如MOS晶体管的电子器件的方法，包括以下步骤：在电功能衬底上形成多个半导体岛，在第一半导体岛子集上或第二子体上印刷第一介电层， 在半导体岛的第二子集上或之上，以及退火。 第一介电层包含第一掺杂剂，并且（任选的）第二介电层包含不同于第一掺杂剂的第二掺杂剂。 电介质层，半导体岛和衬底被充分退火以将第一掺杂剂扩散到半导体岛的第一子集中，并且当存在时将第二掺杂剂扩散到半导体岛的第二子集中。