公开(公告)号：US08222967B1

公开(公告)日：2012-07-17

申请号：US12644128

申请日：2009-12-22

申请人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

发明人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

IPC分类号： H03H7/30 ,  H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/193 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/405 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45686 ,  H03F2203/7236 ,  H03H11/1213 ,  H03H11/48

摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.

摘要翻译： 集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。 每个NMOS级可包括折叠的有源电感电路。 每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化 。 例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。 在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

公开(公告)号：US08816745B1

公开(公告)日：2014-08-26

申请号：US13316361

申请日：2011-12-09

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03L5/00

CPC分类号： H04L25/03878 ,  H03K19/018507

摘要： An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.

摘要翻译： 提供了包括基于电感器和非电感器的均衡器级的均衡器电路。 在一个实现中，均衡器电路包括第一均衡器电路，其包括基于第一电感器的均衡器级和耦合到基于第一电感器的均衡器级的基于非电感器的第一非均衡器级。 在一个实现中，均衡器电路还包括包括多个基于电感器的均衡器级的第二均衡器电路，其中多个基于电感器的均衡器级包括基于第一电感器的均衡器级。 在一个实现中，第一均衡器电路还包括耦合到基于第一电感器的均衡器级和基于非电感器的第一非均衡级的基于第二电感器的均衡器级。

公开(公告)号：US08705605B1

公开(公告)日：2014-04-22

申请号：US13288701

申请日：2011-11-03

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L1/243 ,  H04B17/14 ,  H04L25/03878 ,  H04W52/0274 ,  Y02D70/00

摘要： Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.

摘要翻译： 提供了集成电路（IC）中串行回送测试的设备和方法。 为了实现环回测试，IC的接收机的均衡器级掉电。 此外，均衡器级的共模电压被减小和/或均衡器级的体积节点连接到地。 这样做可以减少来自缓冲器的输入引脚的电容耦合的影响，从而提高环回输出信号的质量。

公开(公告)号：US07454645B2

公开(公告)日：2008-11-18

申请号：US11097527

申请日：2005-03-31

申请人： Gabriel M. Li ,  Greg J. Richmond ,  Sangeeta Raman

发明人： Gabriel M. Li ,  Greg J. Richmond ,  Sangeeta Raman

IPC分类号： G06F1/00 ,  G06F1/14

CPC分类号： H03K5/26 ,  G01R23/005 ,  G06F1/12 ,  H03K5/19

摘要： A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

摘要翻译： 本文提供了一种用于监视时钟信号的状态的电路和方法。 通常，该方法可以包括将一对时钟信号提供给时钟监控电路，时钟监视电路被配置为监视相对于另一个时钟信号的一个时钟信号的状态。 该状态指示一个时钟信号的频率是否比其他时钟信号的频率更快，更慢或基本上等于其他时钟信号的频率。 一旦确定，状态可以作为位模式存储在状态寄存器内，状态寄存器可操作地耦合到时钟监视器电路。 这样可以通过检测状态寄存器中的一个或多个位的逻辑状态来读取状态。

公开(公告)号：US20060224910A1

公开(公告)日：2006-10-05

申请号：US11097527

申请日：2005-03-31

申请人： Gabriel Li ,  Greg Richmond ,  Sangeeta Raman

发明人： Gabriel Li ,  Greg Richmond ,  Sangeeta Raman

IPC分类号： G06F1/00

CPC分类号： H03K5/26 ,  G01R23/005 ,  G06F1/12 ,  H03K5/19

摘要： A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

摘要翻译： 本文提供了一种用于监视时钟信号的状态的电路和方法。 通常，该方法可以包括将一对时钟信号提供给时钟监控电路，时钟监视电路被配置为监视相对于另一个时钟信号的一个时钟信号的状态。 该状态指示一个时钟信号的频率是否比其他时钟信号的频率更快，更慢或基本上等于其他时钟信号的频率。 一旦确定，状态可以作为位模式存储在状态寄存器内，状态寄存器可操作地耦合到时钟监视器电路。 这样可以通过检测状态寄存器中的一个或多个位的逻辑状态来读取状态。