公开(公告)号：US08222967B1

公开(公告)日：2012-07-17

申请号：US12644128

申请日：2009-12-22

申请人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

发明人： Sangeeta Raman ,  Tim Tri Hoang ,  Sergey Yuryevich Shumarayev

IPC分类号： H03H7/30 ,  H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/193 ,  H03F3/45197 ,  H03F3/45475 ,  H03F3/72 ,  H03F2200/405 ,  H03F2203/45488 ,  H03F2203/45494 ,  H03F2203/45686 ,  H03F2203/7236 ,  H03H11/1213 ,  H03H11/48

摘要： Equalizer circuitry on an integrated circuit (“IC”) includes a plurality of NMOS equalizer stages connected in series. Each NMOS stage may include folded active inductor circuitry. Each NMOS stage may also include various circuit elements having controllably variable circuit parameters so that the equalizer can be controllably adapted to perform for any of a wide range of high-speed serial data signal bit rates and other variations of communication protocols and/or communication conditions. For example, each NMOS stage may be programmable to control at least one of bandwidth and power consumption of the equalizer circuitry. The equalizer may also have a first PMOS stage that can be used instead of the first NMOS stage in cases in which the voltage of the incoming signal to be equalized is too low for an initial NMOS stage.

摘要翻译： 集成电路（“IC”）上的均衡器电路包括串联连接的多个NMOS均衡器级。 每个NMOS级可包括折叠的有源电感电路。 每个NMOS级还可以包括具有可控制的可变电路参数的各种电路元件，使得均衡器可被可控地适用于执行宽范围的高速串行数据信号比特率和通信协议和/或通信条件的其它变化 。 例如，每个NMOS级可以是可编程的，以控制均衡器电路的带宽和功耗中的至少一个。 在均衡的输入信号的电压对于初始NMOS级来说太低的情况下，均衡器也可以具有第一PMOS级，而不用第一NMOS级。

公开(公告)号：US08816745B1

公开(公告)日：2014-08-26

申请号：US13316361

申请日：2011-12-09

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03L5/00

CPC分类号： H04L25/03878 ,  H03K19/018507

摘要： An equalizer circuitry that includes both inductor based and non-inductor based equalizer stages is provided. In one implementation, the equalizer circuitry includes a first equalizer circuitry including a first inductor based equalizer stage and a first non-inductor based equalizer stage coupled to the first inductor based equalizer stage. In one implementation, the equalizer circuitry further includes a second equalizer circuitry including a plurality of inductor based equalizer stages, where the plurality of inductor based equalizer stages includes the first inductor based equalizer stage. In one implementation, the first equalizer circuitry further includes a second inductor based equalizer stage coupled to the first inductor based equalizer stage and the first non-inductor based equalize stage.

摘要翻译： 提供了包括基于电感器和非电感器的均衡器级的均衡器电路。 在一个实现中，均衡器电路包括第一均衡器电路，其包括基于第一电感器的均衡器级和耦合到基于第一电感器的均衡器级的基于非电感器的第一非均衡器级。 在一个实现中，均衡器电路还包括包括多个基于电感器的均衡器级的第二均衡器电路，其中多个基于电感器的均衡器级包括基于第一电感器的均衡器级。 在一个实现中，第一均衡器电路还包括耦合到基于第一电感器的均衡器级和基于非电感器的第一非均衡级的基于第二电感器的均衡器级。

公开(公告)号：US08705605B1

公开(公告)日：2014-04-22

申请号：US13288701

申请日：2011-11-03

申请人： Sangeeta Raman ,  Tim Tri Hoang

发明人： Sangeeta Raman ,  Tim Tri Hoang

IPC分类号： H03K5/159 ,  H03H7/30 ,  H03H7/40

CPC分类号： H04L1/243 ,  H04B17/14 ,  H04L25/03878 ,  H04W52/0274 ,  Y02D70/00

摘要： Devices and methods for serial loopback testing in an integrated circuit (IC) are provided. To implement loopback testing, an equalizer stage of a receiver of the IC is powered down. In addition, the common-mode voltage of the equalizer stage is reduced and/or a bulk node of the equalizer stage is connected to ground. Doing so may reduce the impact of capacitive coupling from the input pins of buffer, thereby improving the quality of the loopback output signal.

摘要翻译： 提供了集成电路（IC）中串行回送测试的设备和方法。 为了实现环回测试，IC的接收机的均衡器级掉电。 此外，均衡器级的共模电压被减小和/或均衡器级的体积节点连接到地。 这样做可以减少来自缓冲器的输入引脚的电容耦合的影响，从而提高环回输出信号的质量。

公开(公告)号：US10110328B2

公开(公告)日：2018-10-23

申请号：US13446555

申请日：2012-04-13

申请人： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

发明人： Neville Carvalho ,  Tim Tri Hoang ,  Sergey Shumarayev

IPC分类号： G01R35/00 ,  H04B17/21 ,  H04B17/11 ,  G12B13/00

摘要： The present disclosure provides apparatus and methods for the calibration of analog circuitry on an integrated circuit. One embodiment relates to a method of calibrating analog circuitry within an integrated circuit. A microcontroller that is embedded in the integrated circuit is booted up. A reset control signal is sent to reset an analog circuit in the integrated circuit, and a response signal for the analog circuit is monitored by the microcontroller. Based on the response signal, a calibration parameter for the analog circuit is determined, and the analog circuit is configured using the calibration parameter. Other embodiments, aspects and features are also disclosed.

公开(公告)号：US09559881B2

公开(公告)日：2017-01-31

申请号：US12283652

申请日：2008-09-15

申请人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

发明人： Neville Carvalho ,  Allan Thomas Davidson ,  Andy Turudic ,  Bruce B. Pedersen ,  David W. Mendel ,  Kalyan Kankipati ,  Michael Menghui Zheng ,  Sergey Shumarayev ,  Seungmyon Park ,  Tim Tri Hoang ,  Kumara Tharmalingam

IPC分类号： H04L7/00 ,  H04B1/38 ,  H04L25/14

CPC分类号： H04L25/14

摘要： A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner.

摘要翻译： 描述了具有降低的等待时间不确定性的收发机系统。 在一个实现中，收发器系统具有字对齐器等待时间不确定度为零。 在另一个实现中，收发器系统具有接收器到发射器的传输等待时间不确定度为零。 在另一个实现中，收发器系统具有字对齐器延迟不确定度为零和接收器到发射器的传输等待时间不确定度为零。 在一个具体实现中，通过在发射机锁相环（PLL）中使用发射机并行时钟作为反馈信号来消除接收机到发射机的传输等待时间不确定性。 在一个实现中，这通过可选地使发射机分频器（其产生发射机并行时钟）作为发射机PLL的反馈路径的一部分来实现。 在一个实施方案中，通过使用位拖动器以这样的方式滑动位来消除字对齐器延迟不确定性，使得由于字对齐和位滑动引起的总延迟对于恢复时钟的所有阶段是恒定的。 这允许在由解串器的并行化的所有阶段的位的接收和传输之间具有固定和已知的等待时间。 在一个具体实现中，由于位对准器的位移和由位拖动器的位滑动导致的总延迟为零，因为位拖动器滑动位，以补偿由字对准器执行的位移。

公开(公告)号：US08976804B1

公开(公告)日：2015-03-10

申请号：US13041764

申请日：2011-03-07

申请人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04L12/66

CPC分类号： H03K19/17744

摘要： In a programmable logic device with a number of different types of serial interfaces, different power supply filtering schemes are applied to different interfaces. For interfaces operating at the lowest data rates—e.g., 1 Gbps—circuit-board level filtering including one or more decoupling capacitors may be provided. For interfaces operating at somewhat higher data rates—e.g., 3 Gbps—modest on-package filtering also may be provided, which may include power-island decoupling. For interfaces operating at still higher data rates—e.g., 6 Gbps—more substantial on-package filtering, including one or more on-package decoupling capacitors, also may be provided. For interfaces operating at the highest data rates—e.g., 10 Gbps—on-die filtering, which may include one or more on-die filtering or regulating networks, may be provided. The on-die regulators may be programmably bypassable allowing a user to trade off performance for power savings.

摘要翻译： 在具有多种不同类型的串行接口的可编程逻辑器件中，不同的电源滤波方案被应用于不同的接口。 对于以最低数据速率操作的接口，例如，可以提供包括一个或多个去耦电容器的1Gbps电路板电平滤波器。 对于以较高数据速率工作的接口，例如，也可以提供3 Gbps适度的封装内滤波，这可能包括功率岛解耦。 对于以更高的数据速率运行的接口，例如，也可以提供包括一个或多个封装内去耦电容器的6Gbps更实质的封装内滤波。 对于以最高数据速率工作的接口，例如，可以提供10Gbps片上滤波，其可以包括一个或多个片上滤波或调节网络。 片上调节器可以可编程地旁路，允许用户权衡功能以节省功率。

公开(公告)号：US08653853B1

公开(公告)日：2014-02-18

申请号：US11618828

申请日：2006-12-31

申请人： Sergey Shumarayev ,  Tim Tri Hoang ,  Lawrence David Smith

发明人： Sergey Shumarayev ,  Tim Tri Hoang ,  Lawrence David Smith

IPC分类号： H03K19/0175

CPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1084 ,  H03K19/17744 ,  H03K19/17784 ,  H03K19/17788

摘要： Techniques are provided for transmitting signals through a differential interface between circuits in different power supply domains. A driver circuit in a first power supply domain converts single-ended signals into differential signals. The driver circuit then transmits the differential signals to a receiver circuit in a second power supply domain. The receiver circuit converts the differential signals back into single-ended signals for transmission to circuit elements in the second power supply domain. The differential interface reduces the transmission of noise between circuit elements in the first power supply domain and circuit elements in the second power supply domain.

摘要翻译： 提供了用于通过不同电源域中的电路之间的差分接口传输信号的技术。 第一电源域中的驱动电路将单端信号转换成差分信号。 然后，驱动器电路将差分信号发送到第二电源域中的接收器电路。 接收器电路将差分信号转换回单端信号以传输到第二电源域中的电路元件。 差分接口减少了第一电源域中的电路元件与第二电源域中的电路元件之间的噪声传输。

公开(公告)号：US08464088B1

公开(公告)日：2013-06-11

申请号：US12915794

申请日：2010-10-29

申请人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

发明人： Toan Thanh Nguyen ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Weiqi Ding ,  Thungoc M. Tran

IPC分类号： G06F1/04

CPC分类号： G06F1/04 ,  G06F1/10

摘要： Various methods and structures related to clock distribution for flexible channel bonding are disclosed. One embodiment provides a clock network in physical media attachment (“PMA”) circuitry, a specific type or portion of system interconnect circuitry, arranged in pairs of channel groups. In one embodiment, clock generation circuitry blocks (“CGBs”) in each pair of channel groups receives outputs of multiple phased locked loop circuits (“PLLs”) which can be selectively utilized by the CGBs to generate PMA clock signals. In another embodiment, the CGBs can also select output of a clock data recovery (“CDR”)/transmit PLL circuitry block in one of the channels of a channel group of the pair of channel groups. In one embodiment, first groups of connection lines couple circuitry in a channel group pair such that a designated CGB in each channel group pair can provide clock signals to one or more of the channels in the channel group pair. In one embodiment, second groups of connection lines connect channels in one channel group pair to channels in other channel group pairs such that one or more channels across the channel group pairs can receive a clock signal generated by a CGB in a designated channel. These and other embodiments are described more fully in the disclosure.

摘要翻译： 公开了与用于柔性通道结合的时钟分配有关的各种方法和结构。 一个实施例提供物理介质连接（“PMA”）电路中的时钟网络，系统互连电路的特定类型或部分，被布置成成对的信道组。 在一个实施例中，每对信道组中的时钟产生电路块（“CGB”）接收多个锁相环电路（“PLL”）的输出，这些电路可被CGB选择性地用于产生PMA时钟信号。 在另一个实施例中，CGB还可以在一对信道组的信道组的信道之一中选择时钟数据恢复（“CDR”）/发送PLL电路块的输出。 在一个实施例中，第一组连接线将信道组对中的电路耦合，使得每个信道组对中的指定CGB可以向信道组对中的一个或多个信道提供时钟信号。 在一个实施例中，第二组连接线将一个信道组对中的信道与其它信道组对中的信道相连，使得跨信道组对的一个或多个信道可以接收由指定信道中的CGB产生的时钟信号。 在本公开中更全面地描述了这些和其它实施例。

公开(公告)号：US08416845B1

公开(公告)日：2013-04-09

申请号：US11484285

申请日：2006-07-11

申请人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

发明人： Wilson Wong ,  Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  Tim Tri Hoang

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03057 ,  H03K5/1532

摘要： Methods and circuits for automatic adjustment of equalization are presented that improve the quality of equalization for input signals with varying amplitudes. The methods and circuits may be used in Decision Feedback Equalization (DFE) circuits to maintain a constant equalization boost amplitude despite variations in input signal amplitude. The equalization circuitry measures the amplitude of the equalization input signal and computes tap coefficients to maintain a desired level of boost amplitude. Tap coefficients may be automatically adjusted by the equalization circuitry.

摘要翻译： 提出了用于自动调整均衡的方法和电路，其提高具有变化幅度的输入信号的均衡质量。 方法和电路可以用于判决反馈均衡（DFE）电路中，以维持恒定的均衡提升幅度，尽管输入信号幅度有变化。 均衡电路测量均衡输入信号的幅度并计算抽头系数以维持期望的升压幅度。 抽头系数可以由均衡电路自动调整。

公开(公告)号：US08208523B2

公开(公告)日：2012-06-26

申请号：US13079420

申请日：2011-04-04

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。