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    One-transistor memory cell with bias gate
    1.
    发明申请
    One-transistor memory cell with bias gate 有权
    具有偏置栅极的单晶体管存储单元

    公开(公告)号：US20080061346A1

    公开(公告)日：2008-03-13

    申请号：US11516814

    申请日：2006-09-07

    申请人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    发明人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    IPC分类号： H01L29/76 ,  G11C11/24 ,  G11C11/34

    CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

    摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。

    Integrated circuits and methods of forming a field effect transistor
    2.
    发明授权
    Integrated circuits and methods of forming a field effect transistor 有权
    集成电路和形成场效应晶体管的方法

    公开(公告)号：US07244659B2

    公开(公告)日：2007-07-17

    申请号：US11076774

    申请日：2005-03-10

    申请人： Sanh D. Tang ,  Gordon Haller

    发明人： Sanh D. Tang ,  Gordon Haller

    IPC分类号： H01L21/76

    CPC分类号： H01L29/0653 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

    摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

    摘要翻译： 公开了形成场效应晶体管的集成电路和方法。 在一个方面，集成电路包括包括本体半导体材料的半导体衬底。 电绝缘材料容纳在本体半导体材料内。 在绝缘材料上形成半导体材料。 包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。 在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。 在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。 公开了其他方面和实施方式，包括方法方面。

    Methods of fabricating a memory device
    3.
    发明授权
    Methods of fabricating a memory device 有权
    制造存储器件的方法

    公开(公告)号：US08222105B2

    公开(公告)日：2012-07-17

    申请号：US12703502

    申请日：2010-02-10

    申请人： Gordon Haller ,  Sanh D. Tang ,  Steve Cummings

    发明人： Gordon Haller ,  Sanh D. Tang ,  Steve Cummings

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823487 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10888

    摘要： A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced.

    摘要翻译： 包括垂直晶体管的存储器件包括直接耦合到每个存储器单元的源极区域的数字线。 由于不使用电插头来形成数字线和源极区之间的接触，所以可以减少多个制造步骤，并且还可以减少制造缺陷的可能性。 在一些实施例中，存储器件可以包括垂直晶体管，其具有从硅衬底的上部凹陷的栅极区域。 随着从硅衬底凹入的栅极区域，栅极区域与源极/漏极区域进一步间隔开，因此，可以减小栅极区域和源极/漏极区域之间的交叉电容。

    One-transistor memory cell with bias gate
    4.
    发明授权
    One-transistor memory cell with bias gate 有权
    具有偏置栅极的单晶体管存储单元

    公开(公告)号：US07589995B2

    公开(公告)日：2009-09-15

    申请号：US11516814

    申请日：2006-09-07

    申请人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    发明人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

    摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。

    System and method for fabricating a fin field effect transistor
    6.
    发明授权
    System and method for fabricating a fin field effect transistor 有权
    用于制造鳍式场效应晶体管的系统和方法

    公开(公告)号：US07745319B2

    公开(公告)日：2010-06-29

    申请号：US11508047

    申请日：2006-08-22

    申请人： Sanh D. Tang ,  Gordon Haller

    发明人： Sanh D. Tang ,  Gordon Haller

    IPC分类号： H01L21/428

    CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

    摘要： There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.

    摘要翻译： 提供了制造鳍式场效应晶体管的系统和方法。 更具体地，在一个实施例中，提供了一种方法，包括在衬底上沉积氮化物层，在氮化层上施加光刻掩模以限定壁的位置，蚀刻氮化物层以产生壁，去除 光刻掩模，在壁附近沉积间隔层，蚀刻间隔层以产生邻近壁的隔离物，其中间隔物和壁覆盖基底的第一部分，并蚀刻未被覆盖的基底的第二部分 通过间隔件形成沟槽。

    Integrated circuits
    7.
    发明授权
    Integrated circuits 有权
    集成电路

    公开(公告)号：US07687857B2

    公开(公告)日：2010-03-30

    申请号：US11957013

    申请日：2007-12-14

    申请人： Sanh D. Tang ,  Gordon Haller

    发明人： Sanh D. Tang ,  Gordon Haller

    IPC分类号： H01L29/786

    CPC分类号： H01L29/0653 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

    摘要： Integrated circuits and methods of forming field effect transistors are disclosed. In one aspect, an integrated circuit includes a semiconductor substrate comprising bulk semiconductive material. Electrically insulative material is received within the bulk semiconductive material. Semiconductor material is formed on the insulative material. A field effect transistor is included and comprises a gate, a channel region, and a pair of source/drain regions. In one implementation, one of the source/drain regions is formed in the semiconductor material, and the other of the source/drain regions is formed in the bulk semiconductive material. In one implementation, the electrically insulative material extends from beneath one of the source/drain regions to beneath only a portion of the channel region. Other aspects and implementations, including methodical aspects, are disclosed.

    摘要翻译： 公开了形成场效应晶体管的集成电路和方法。 在一个方面，集成电路包括包括本体半导体材料的半导体衬底。 电绝缘材料容纳在本体半导体材料内。 在绝缘材料上形成半导体材料。 包括场效应晶体管，并包括栅极，沟道区和一对源极/漏极区。 在一个实施方案中，源/漏区中的一个形成在半导体材料中，并且源/漏区中的另一个在体半导体材料中形成。 在一个实施方案中，电绝缘材料从源极/漏极区域之一延伸到仅沟道区域的仅一部分的下方。 公开了其他方面和实施方式，包括方法方面。

    System and method for fabricating a fin field effect transistor
    8.
    发明申请
    System and method for fabricating a fin field effect transistor 有权
    用于制造鳍式场效应晶体管的系统和方法

    公开(公告)号：US20080050885A1

    公开(公告)日：2008-02-28

    申请号：US11508047

    申请日：2006-08-22

    申请人： Sanh D. Tang ,  Gordon Haller

    发明人： Sanh D. Tang ,  Gordon Haller

    IPC分类号： H01L21/76

    CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

    摘要： There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.

    摘要翻译： 提供了制造鳍式场效应晶体管的系统和方法。 更具体地，在一个实施例中，提供了一种方法，包括在衬底上沉积氮化物层，在氮化层上施加光刻掩模以限定壁的位置，蚀刻氮化物层以产生壁，去除 光刻掩模，在壁附近沉积间隔层，蚀刻间隔层以产生邻近壁的隔离物，其中间隔物和壁覆盖基底的第一部分，并蚀刻未被覆盖的基底的第二部分 通过间隔件形成沟槽。

    FIN STRUCTURES AND METHODS OF FABRICATING FIN STRUCTURES
    9.
    发明申请
    FIN STRUCTURES AND METHODS OF FABRICATING FIN STRUCTURES 有权
    FIN结构和FIN结构的制作方法

    公开(公告)号：US20100252886A1

    公开(公告)日：2010-10-07

    申请号：US12795495

    申请日：2010-06-07

    申请人： Sanh D. Tang ,  Gordon Haller

    发明人： Sanh D. Tang ,  Gordon Haller

    IPC分类号： H01L27/088 ,  H01L21/762 ,  H01L21/28

    CPC分类号： H01L29/785 ,  H01L21/3086 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

    摘要： There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins.

    摘要翻译： 提供了用于制造翅片结构的翅片结构和方法。 更具体地，翅片结构形成在基板中。 翅片结构可以包括由通道分开的两个翅片，其中翅片可以用作场效应晶体管的翅片。 翅片结构形成在衬底的上表面下方，并且可以在不利用光刻掩模来形成以蚀刻鳍片的情况下形成。

    One Transistor Memory Cell with Bias Gate
    10.
    发明申请
    One Transistor Memory Cell with Bias Gate 有权
    一个具有偏置门的晶体管存储单元

    公开(公告)号：US20090311845A1

    公开(公告)日：2009-12-17

    申请号：US12537470

    申请日：2009-08-07

    申请人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    发明人： Sanh D. Tang ,  Gordon Haller ,  Daniel H. Doyle

    IPC分类号： H01L21/76

    CPC分类号： H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

    摘要： One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

    摘要翻译： 单晶体管（1T）无电容器DRAM单元各自包括具有将浮体区域与基底基板分离的偏置栅极层的MOS晶体管。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。