Flexible mesh structure for hierarchical scheduling
    2.
    发明授权
    Flexible mesh structure for hierarchical scheduling 有权
    灵活的网格结构,用于分层调度

    公开(公告)号:US07460544B2

    公开(公告)日:2008-12-02

    申请号:US11024957

    申请日:2004-12-29

    IPC分类号: H04L12/28

    CPC分类号: H04L47/24 H04L47/50

    摘要: Systems and methods employing a flexible mesh structure for hierarchical scheduling are disclosed. The method generally includes reading a packet grouping configured in a two dimensional mesh structure of N columns, each containing M packets, selecting and promoting a column best packet from each column to a final row containing N packets, reading, selecting and promoting a final best packet from the final row to a next level in the hierarchy. Each time a final best packet is selected and promoted, the mesh structure can be refreshed by replacing the packet corresponding to the final best packet, and reading, selecting and promoting a column best packet from the column containing the replacement packet to the final row. As only the column containing the replacement packet and the final row are read and compared for each refresh, the mesh structure results in reduced read and compare cycles for schedule determination.

    摘要翻译: 公开了采用柔性网格结构进行分层调度的系统和方法。 该方法通常包括读取以N列的二维网格结构配置的分组分组,每个分组包含M个分组,从每列选择并提升列最佳分组到包含N个分组的最后一行,读取,选择和促进最终最佳 分组从最后一行到层次结构中的下一个级别。 每次选择和提升最终最佳分组时,可以通过替换与最终最佳分组相对应的分组来刷新网格结构,并从包含替换分组的列到最后一行读取,选择和促进列最佳分组。 由于只有包含替换数据包和最后一行的列被读取并进行比较才能进行每次刷新,所以网格结构导致读取和比较周期减少以用于计划确定。

    Processor having content addressable memory for block-based queue structures
    3.
    发明授权
    Processor having content addressable memory for block-based queue structures 有权
    具有内容可寻址存储器的处理器,用于基于块的队列结构

    公开(公告)号:US07467256B2

    公开(公告)日:2008-12-16

    申请号:US11027601

    申请日:2004-12-28

    IPC分类号: G06F12/00

    摘要: Queuing command information is stored in a content addressable memory (CAM) where a queuing command for a first queue is received, the CAM is examined to determine if commands for the first queue are present, and if commands for the first queue were found to be present, information is stored in a linked list for the received command in multiple CAM entries.

    摘要翻译: 排队命令信息存储在内容可寻址存储器(CAM)中,其中接收到用于第一队列的排队命令,检查CAM以确定是否存在用于第一队列的命令,并且如果发现第一队列的命令是 在多个CAM条目中,信息被存储在所接收的命令的链表中。

    Program memory having flexible data storage capabilities
    6.
    发明申请
    Program memory having flexible data storage capabilities 审中-公开
    具有灵活数据存储功能的程序存储器

    公开(公告)号:US20080022175A1

    公开(公告)日:2008-01-24

    申请号:US11478393

    申请日:2006-06-29

    IPC分类号: G01R31/28

    摘要: A method according to one embodiment may include performing one or more fetch operations to retrieve one or more instructions from a program memory; scheduling a write instruction to write data from at least one data register into the program memory; and stealing one or more cycles from one or more of the fetch operations to write the data in the at least one data register into the program memory. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

    摘要翻译: 根据一个实施例的方法可以包括执行一个或多个提取操作以从程序存储器检索一个或多个指令; 调度写指令以将数据从至少一个数据寄存器写入程序存储器; 以及从一个或多个获取操作中窃取一个或多个周期,以将所述至少一个数据寄存器中的数据写入程序存储器。 当然,在不偏离本实施例的情况下,可以进行许多替代,变化和修改。

    Method and apparatus providing efficient queue descriptor memory access
    7.
    发明授权
    Method and apparatus providing efficient queue descriptor memory access 有权
    提供有效的队列描述符存储器访问的方法和装置

    公开(公告)号:US07277990B2

    公开(公告)日:2007-10-02

    申请号:US10955969

    申请日:2004-09-30

    IPC分类号: G06F12/00

    CPC分类号: G06F12/121

    摘要: A system having queue control structures includes a conflict avoidance mechanism to prevent memory bank conflicts for queue descriptor access. In one embodiment, a queue descriptor bank table contains information including in which memory bank each queue descriptor is stored.

    摘要翻译: 具有队列控制结构的系统包括冲突避免机制,以防止存储器组冲突用于队列描述符访问。 在一个实施例中,队列描述符库表包含包含存储每个队列描述符的存储体的信息。

    Digest generation
    10.
    发明授权
    Digest generation 有权
    消化一代

    公开(公告)号:US09292548B2

    公开(公告)日:2016-03-22

    申请号:US13995236

    申请日:2011-11-01

    IPC分类号: G06F17/30

    摘要: In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.

    摘要翻译: 在一个实施例中,电路可以生成待组合的摘要以产生散列值。 摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。 电路可以包括循环冗余校验(CRC)发生器电路,以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。 所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。 在不脱离本实施例的情况下,可以进行许多修改,变型和替换。