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    TECHNOLOGIES FOR PROVIDING DEFERRED ERROR RECORDS TO AN ERROR HANDLER
    2.
    发明申请
    TECHNOLOGIES FOR PROVIDING DEFERRED ERROR RECORDS TO AN ERROR HANDLER 审中-公开
    将提示错误记录提供给错误处理的技术

    公开(公告)号：US20140188829A1

    公开(公告)日：2014-07-03

    申请号：US13728451

    申请日：2012-12-27

    申请人： Narayan Ranganathan ,  Mahesh Natu ,  Mohan J. Kumar ,  Sarathy Jayakumar

    发明人： Narayan Ranganathan ,  Mahesh Natu ,  Mohan J. Kumar ,  Sarathy Jayakumar

    IPC分类号： G06F17/30

    CPC分类号： G06F16/21

    摘要： Technologies to generate an error record are described herein. A method includes performing a scan of one or more error logs to identify a source of data in response to an attempt to access the data, determining whether an amount of time to complete the scan will exceed a threshold value, and generating a notice that the error record will be deferred based on the determination. A system includes a data collector to scan one or more error logs to identify a source of data in response to an attempt to access the data, a controller to determine whether an amount of time to scan the error logs to identify the source of data will exceed a threshold value, and a signal generator to generate a signal indicating that the error record is to be deferred based on the determination.

    摘要翻译： 本文描述了生成错误记录的技术。 一种方法包括：响应于访问数据的尝试，执行一个或多个错误日志的扫描以识别数据源，确定完成扫描的时间量是否将超过阈值，以及生成通知 错误记录将根据确定推迟。 系统包括数据收集器，用于扫描一个或多个错误日志以响应于访问数据的尝试来识别数据源;控制器，用于确定扫描错误日志以识别数据源的时间量是否将 超过阈值，以及信号发生器，用于基于该确定产生指示错误记录被延迟的信号。

    FAST CACHE FLUSH
    6.
    发明申请
    FAST CACHE FLUSH 有权
    快速缓存

    公开(公告)号：US20150161037A1

    公开(公告)日：2015-06-11

    申请号：US14100721

    申请日：2013-12-09

    申请人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

    发明人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Eswaramoorthi Nallusamy

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/1032 ,  G06F2212/7203

    摘要： Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in a volatile memory, determine whether the first data element is to be stored in a nonvolatile memory, and in response to a determination that the first data element is to be stored in a nonvolatile memory, to forward the first transaction to the memory controller coupled to the nonvolatile memory. Other examples are also disclosed and claimed.

    摘要翻译： 描述了管理存储器操作的装置，系统和方法。 在一个示例中，控制器包括接收第一事务以操作易失性存储器中的第一数据元素的逻辑，确定第一数据元素是否要存储在非易失性存储器中，并且响应于确定第一数据 元件将被存储在非易失性存储器中，以将第一事务转发到耦合到非易失性存储器的存储器控​​制器。 还公开并要求保护其他实例。

    SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS
    7.
    发明申请
    SYSTEM MANAGEMENT INTERRUPT HANDLING FOR MULTI-CORE PROCESSORS 有权
    多核处理器的系统管理中断处理

    公开(公告)号：US20140281092A1

    公开(公告)日：2014-09-18

    申请号：US13799327

    申请日：2013-03-13

    申请人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

    发明人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Michael D. Kinney

    IPC分类号： G06F13/24

    CPC分类号： G06F9/4812 ,  G06F11/0772

    摘要： Technologies for system management interrupt (“SMI”) handling include a number of processor cores configured to enter a system management mode (“SMM”) in response to detecting an SMI. The first processor core to enter SMM and acquire a master thread lock sets an in-progress flag and executes a master SMI handler without waiting for other processor cores to enter SMM. Other processor cores execute a subordinate SMI handler. The master SMI handler may direct the subordinate SMI handlers to handle core-specific SMIs. The multi-core processor may set an SMI service pending flag in response to detecting the SMI, which is cleared by the processor core that acquires the master thread lock. A processor core entering SMM may immediately resume normal execution upon determining the in-progress flag is not set and the service pending flag is not set, to detect and mitigate spurious SMIs. Other embodiments are described and claimed.

    摘要翻译： 用于系统管理中断（“SMI”）处理的技术包括配置为响应于检测到SMI而进入系统管理模式（“SMM”）的多个处理器核心。 进入SMM并获取主线程锁的第一个处理器核心设置正在进行的标志，并执行主SMI处理程序，而不必等待其他处理器内核进入SMM。 其他处理器核心执行从属SMI处理程序。 主SMI处理程序可以指示下级SMI处理程序来处理核心特定的SMI。 响应于检测到由获取主线程锁的处理器核心清除的SMI，多核处理器可以设置SMI服务挂起标志。 进入SMM的处理器核心在确定进行中标志未被设置并且未设置服务暂挂标志时，可以立即恢复正常执行，以检测和减轻假SMI。 描述和要求保护其他实施例。

    RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS
    8.
    发明申请
    RECOVERY AFTER INPUT/OUPUT ERROR-CONTAINMENT EVENTS 有权
    INPUT / OUPUT ERROR-CONTAINENT事件后恢复

    公开(公告)号：US20130332781A1

    公开(公告)日：2013-12-12

    申请号：US13997870

    申请日：2012-06-06

    申请人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

    发明人： Sarathy Jayakumar ,  Mohan J. Kumar ,  Jose A. Vargas

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0751 ,  G06F11/0712 ,  G06F11/0745 ,  G06F11/0793

    摘要： Embodiments of apparatus, computer-implemented methods, systems, devices, and computer-readable media are described herein for a computing device with a platform entity such as an interrupt handier configured to notify an operating system or virtual machine monitor executing on the computing device of an input/output error-containment event. In various embodiments, the interrupt handler may be configured to facilitate recovery of a link to an input/output device that caused the input/output error-containment event, responsive to a directive from the operating system or virtual machine monitor.

    摘要翻译： 本文描述了具有平台实体的计算设备，例如中断处理器的设备，计算机实现的方法，系统，设备和计算机可读介质的实施例，其被配置为通知在计算设备上执行的操作系统或虚拟机监视器 输入/输出错误容纳事件。 在各种实施例中，响应于来自操作系统或虚拟机监视器的指示，中断处理程序可以被配置为便于恢复导致输入/输出错误容纳事件的输入/输出设备的链接。

    SECURE AND EFFICIENT MICROCODE(UCODE) HOT-UPGRADE FOR BARE METAL CLOUD
    9.
    发明申请
    SECURE AND EFFICIENT MICROCODE(UCODE) HOT-UPGRADE FOR BARE METAL CLOUD 有权

    公开(公告)号：US20210096848A1

    公开(公告)日：2021-04-01

    申请号：US17120072

    申请日：2020-12-11

    申请人： Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

    发明人： Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

    IPC分类号： G06F8/656 ,  G06F9/48 ,  G06F9/4401 ,  G06F9/455 ,  G06F12/1027

    摘要： A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller (e.g., baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.