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公开(公告)号：US06946704B2
公开(公告)日：2005-09-20
申请号：US10808510
申请日：2004-03-25
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
摘要翻译： 半导体存储单元及其形成方法利用垂直选择晶体管来消除利用相位变化的现有技术的存储单元中的大的单元表面积的问题。 通过本发明实现了具有比现有技术的DRAM器件更小的表面积的存储单元。 除了读取操作中的低功耗之外，本发明还提供即使在写入操作期间具有低功耗的相变存储器。 相变存储器也具有稳定的读出操作。
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公开(公告)号：US07719870B2
公开(公告)日：2010-05-18
申请号：US11976532
申请日：2007-10-25
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管 。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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公开(公告)号：US07341892B2
公开(公告)日：2008-03-11
申请号：US11368603
申请日：2006-03-07
IPC分类号： H01L21/82
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
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公开(公告)号：US07116593B2
公开(公告)日：2006-10-03
申请号：US10485566
申请日：2002-09-13
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由存储单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时，根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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公开(公告)号：US20060148135A1
公开(公告)日：2006-07-06
申请号：US11368603
申请日：2006-03-07
IPC分类号： H01L21/50
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
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公开(公告)号：US20080121860A1
公开(公告)日：2008-05-29
申请号：US12007851
申请日：2008-01-16
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
摘要翻译： 半导体存储单元及其形成方法利用垂直选择晶体管来消除利用相位变化的现有技术的存储单元中的大的单元表面积的问题。 通过本发明实现了具有比现有技术的DRAM器件更小的表面积的存储单元。 除了读取操作中的低功耗之外，本发明还提供即使在写入操作期间具有低功耗的相变存储器。 相变存储器也具有稳定的读出操作。
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公开(公告)号：US07324372B2
公开(公告)日：2008-01-29
申请号：US11507576
申请日：2006-08-22
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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公开(公告)号：US07078273B2
公开(公告)日：2006-07-18
申请号：US10876461
申请日：2004-06-28
IPC分类号： H01L21/82
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
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公开(公告)号：US20100188877A1
公开(公告)日：2010-07-29
申请号：US12659984
申请日：2010-03-26
IPC分类号： G11C5/06
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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公开(公告)号：US20080062736A1
公开(公告)日：2008-03-13
申请号：US11976532
申请日：2007-10-25
IPC分类号： G11C5/02
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由选择的字线上的所有存储单元中的选择晶体管导通的存储单元中构成的存储器阵列中的未选择的数据线被驱动，每个存储器单元使用依赖于可变电阻的存储元件和选择晶体管 。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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