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    Phase control circuit, semiconductor device and semiconductor memory
    1.
    发明授权
    Phase control circuit, semiconductor device and semiconductor memory 有权

    公开(公告)号：US06222792B1

    公开(公告)日：2001-04-24

    申请号：US09666598

    申请日：2000-09-20

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

    摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US06335901B1

    公开(公告)日：2002-01-01

    申请号：US09531467

    申请日：2000-03-20

    申请人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    发明人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

    摘要翻译： 响应于外部端子（OPT）的第一状态，SDRAM将其操作模式选择为SDR模式，从而释放已经从存储器读出的数据，以响应于由时钟产生的时钟信号 再生电路具有响应于外部端子（OPT）的第二状态而比较电路的输入和输出的相位或选择为DDR模式的功能，从而释放从 响应于与外部时钟信号同步的由时钟信号发生电路产生的时钟信号，存储器垫。

    Phase control circuit, semiconductor device and semiconductor memory
    3.
    发明授权
    Phase control circuit, semiconductor device and semiconductor memory 有权
    相位控制电路，半导体器件和半导体存储器

    公开(公告)号：US06205086B1

    公开(公告)日：2001-03-20

    申请号：US09560724

    申请日：2000-04-28

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

    摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).

    摘要翻译： 相位控制电路包括分别向第一时钟信号（BDA1）分配不同的预定延迟时间的多个固定延迟电路（200-0至200-5）;接收从多个时钟信号输出的时钟信号的检测电路（201） 的固定延迟电路和与其中的第一时钟信号不同的第二时钟信号（PCLK），并产生以多个位表示的检测信号（202），每个位对应于第一时钟信号和第二时钟之间的相位差 信号和可变延迟电路（200-6），其将与每个检测到的信号相对应的相位差延迟到第三时钟信号（BDA2）。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06754133B2

    公开(公告)日：2004-06-22

    申请号：US10231286

    申请日：2002-08-30

    申请人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    发明人： Sadayuki Morita ,  Takeshi Sakata ,  Satoru Hanzawa ,  Takahiro Sonoda ,  Haruko Tadokoro ,  Hiroshi Ichikawa ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076

    摘要： A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

    摘要翻译： 响应于外部终端（OPT）的第一状态，同步动态随机存取存储器（SDRAM）的操作模式选择为单数据速率（SDR）模式，从而释放从存储器中读出的数据 响应于具有比较电路的输入和输出的相位或者被选择为双倍数据速率（DDR）模式的功能的时钟再生电路产生的时钟信号响应于第二状态 外部端子（OPT），从而释放已经从存储器垫读出的数据，响应于与外部时钟同步的时钟信号产生电路产生的时钟信号。 在SDR模式下，数据通过SDRAM中的数据线单向传输，在DDR模式下，数据通过数据线双向传输。

    Semiconductor memory device of DDR configuration having improvement in glitch immunity
    8.
    发明授权
    Semiconductor memory device of DDR configuration having improvement in glitch immunity 有权
    具有提高毛刺抗扰性的DDR配置的半导体存储器件

    公开(公告)号：US06407963B1

    公开(公告)日：2002-06-18

    申请号：US09689664

    申请日：2000-10-13

    申请人： Takahiro Sonoda ,  Takeshi Sakata ,  Sadayuki Morita ,  Yoshinobu Nakagome ,  Haruko Tadokoro ,  Osamu Nagashima

    发明人： Takahiro Sonoda ,  Takeshi Sakata ,  Sadayuki Morita ,  Yoshinobu Nakagome ,  Haruko Tadokoro ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1087 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C8/12

    摘要： A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

    摘要翻译： DDR配置的半导体存储器件提高了毛刺抗扰性，并且提供了使用的便利。 它是一种动态类型的RAM，其内部电路与时钟信号同步地被控制; 提供了一种输入电路，其中在写入操作时输入的第二时钟信号用于将响应于该信号串行输入的多个写数据写入多个第一锁存电路，并且所述第一时钟信号用于采取 写入第一锁存电路的数据进入第二锁存电路，以将它们传送到输入/输出数据总线; 提供逻辑电路，以根据第一时钟信号和第二时钟信号的逻辑屏蔽在第二时钟信号结束时产生的任何噪声，并产生第三时钟信号并将其提供给第一锁存电路 其将写数据输出到至少第二锁存电路的输入。

    Semiconductor integrated circuit device
    10.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US06483349B2

    公开(公告)日：2002-11-19

    申请号：US09987531

    申请日：2001-11-15

    申请人： Takeshi Sakata ,  Hitoshi Tanaka ,  Osamu Nagashima ,  Masafumi Ohi ,  Sadayuki Morita

    发明人： Takeshi Sakata ,  Hitoshi Tanaka ,  Osamu Nagashima ,  Masafumi Ohi ,  Sadayuki Morita

    IPC分类号： A03K190175

    CPC分类号： H03K19/018528

    摘要： Differential amplifier circuits that receive input signals fed through external terminals are served with a first operation voltage and a second operation voltage through a first switching MOSFET and a second switching MOSFET, said first and second switching MOSFETs are turned on by a bis voltage-generating circuit when said input signal is near a central voltage of said first and second operation voltages, control voltages are formed to turn either said first switching MOSFET or said second switching MOSFET on and to turn the other one off to produce a corresponding output signal when the input signal continuously assumes said first voltage or said second voltage for a predetermined period of time, thereby to supply an input signal of a first amplitude corresponding to said first operation voltage and said second operation voltage as well as an input signal of a second amplitude corresponding to a predetermined intermediate voltage between said first operation voltage and said second operation voltage.

    摘要翻译： 接收通过外部端子馈送的输入信号的差分放大器电路通过第一开关MOSFET和第二开关MOSFET被提供第一工作电压和第二工作电压，所述第一和第二开关MOSFET由双电压发生电路 当所述输入信号接近所述第一和第二操作电压的中心电压时，形成控制电压以使所述第一开关MOSFET或所述第二开关MOSFET导通，并将另一个断开以产生相应的输出信号，当输入 信号连续地采取所述第一电压或所述第二电压预定的时间段，从而提供对应于所述第一操作电压和所述第二操作电压的第一幅度的输入信号以及对应于所述第一操作电压的第二幅度的输入信号 所述第一操作电压和所述第二操作电压之间的预定中间电压 工作电压。