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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US06473358B2

    公开(公告)日：2002-10-29

    申请号：US10097564

    申请日：2002-03-15

    申请人： Hiromasa Noda ,  Youji Idei ,  Osamu Nagashima ,  Tetsuo Ado

    发明人： Hiromasa Noda ,  Youji Idei ,  Osamu Nagashima ,  Tetsuo Ado

    IPC分类号： G11C800

    CPC分类号： G11C29/84 ,  G11C7/1027 ,  G11C8/04 ,  G11C11/4087

    摘要： A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.

    摘要翻译： 一种半导体存储器件具有列地址解码器，它包括分别对应于高阶和低阶地址的第一和第二预解码器，用于使用第二预解码器的输出信号作为初始值的移位寄存器，以及 输出电路，用于根据动作模式选择第二预解码器的输出信号或移位寄存器的输出信号。 选择信号由第一预解码器的输出信号和通过输出电路的输出信号形成。 移位寄存器包括用于偶数地址的第一移位寄存器和奇数地址的第二移位寄存器，并且基于顺序动作和交错动作形成位线的两组连续选择信号 通过组合其上下移动动作的初始值。

    Signal generator with synchronous mirror delay circuit
    3.
    发明授权
    Signal generator with synchronous mirror delay circuit 失效
    具有同步镜延迟电路的信号发生器

    公开(公告)号：US5955905A

    公开(公告)日：1999-09-21

    申请号：US967612

    申请日：1997-11-10

    申请人： Youji Idei ,  Masakazu Aoki ,  Hiromasa Noda

    发明人： Youji Idei ,  Masakazu Aoki ,  Hiromasa Noda

    IPC分类号： G11C11/407 ,  G06F1/06 ,  G06F1/10 ,  G11C7/10 ,  H01L27/10 ,  H03K5/135 ,  H04L7/033 ,  H03L7/00

    CPC分类号： H03K5/135 ,  G11C7/1072 ,  H04L7/0331

    摘要： A clock signal received from an external terminal through an input buffer is delayed by delay circuits. A counter circuit is started up in accordance with the clock signal transmitted through the delay circuits to count an oscillation pulse having a frequency which is sufficiently high with respect to that of the clock signal. Further, the counter circuit reversely counts the count in response to a clock signal delayed by one cycle, which has passed through the input buffer. When its count once again reaches the counter value at the start of counting, the counter circuit generates an output timing signal and transmits it to an internal circuit through a clock driver. A delay time outputted from the delay circuits is set to a delay time corresponding to the sum of a delay time of the input buffer and a delay time of the clock driver.

    摘要翻译： 通过输入缓冲器从外部端子接收的时钟信号被延迟电路延迟。 根据通过延迟电路发送的时钟信号启动计数器电路，以对相对于时钟信号的频率足够高的频率的振荡脉冲进行计数。 此外，计数器电路响应延迟了一个周期的时钟信号来反向计数，该周期已经通过输入缓冲器。 当其计数在计数开始时再次达到计数值时，计数器电路产生输出定时信号，并通过时钟驱动器将其发送到内部电路。 从延迟电路输出的延迟时间被设定为对应于输入缓冲器的延迟时间和时钟驱动器的延迟时间之和的延迟时间。

    Semiconductor memory device including a clocking circuit for controlling the read circuit operation
    8.
    发明授权
    Semiconductor memory device including a clocking circuit for controlling the read circuit operation 有权
    半导体存储器件包括用于控制读取电路操作的时钟电路

    公开(公告)号：US6128248A

    公开(公告)日：2000-10-03

    申请号：US345738

    申请日：1999-07-01

    申请人： Youji Idei ,  Masakazu Aoki ,  Hiromasa Noda

    发明人： Youji Idei ,  Masakazu Aoki ,  Hiromasa Noda

    IPC分类号： G11C11/407 ,  G06F1/06 ,  G06F1/10 ,  G11C7/10 ,  H01L27/10 ,  H03K5/135 ,  H04L7/033 ,  G11C8/00

    CPC分类号： H03K5/135 ,  G11C7/1072 ,  H04L7/0331

    摘要： A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock signal and outputs a first internal clock signal delayed from the external clock signal. A second input circuit receives the first internal clock signal and outputs a second internal clock signal delayed from the first internal clock signal. The memory device also includes a circuit which counts a clock signal having a frequency higher than that of the external clock signal and a circuit which starts the counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom. A clock output circuit is provided which outputs a third internal clock signal for controlling the operation of said read circuit based on the timing signal.

    摘要翻译： 提供一种半导体存储器件，其包括存储单元阵列，从所述存储单元阵列读取数据的读取电路和接收外部时钟信号的外部端子。 第一输入电路接收外部时钟信号并输出​​从外部时钟信号延迟的第一内部时钟信号。 第二输入电路接收第一内部时钟信号并输出​​从第一内部时钟信号延迟的第二内部时钟信号。 存储装置还包括对具有高于外部时钟信号的频率的时钟信号进行计数的电路和响应于第二内部时钟信号开始计数的电路，响应于第一内部时钟信号反转所述计数的方向 内部时钟信号，并且检测在所述计数开始时所述计数电路的计数再次达到计数，从而从其输出定时信号。 提供了一种时钟输出电路，其输出用于基于定时信号控制所述读取电路的操作的第三内部时钟信号。

    Memory cell and a memory device having reduced soft error
    9.
    发明授权
    Memory cell and a memory device having reduced soft error 失效
    存储单元和具有降低的软错误的存储器件

    公开(公告)号：US5523966A

    公开(公告)日：1996-06-04

    申请号：US530421

    申请日：1995-09-18

    申请人： Youji Idei ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Toru Masuda ,  Kunihiko Yamaguchi ,  Kenichi Ohhata ,  Takeshi Kusunoki

    发明人： Youji Idei ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Toru Masuda ,  Kunihiko Yamaguchi ,  Kenichi Ohhata ,  Takeshi Kusunoki

    IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

    CPC分类号： G11C11/4125 ,  H01L27/11 ,  H01L27/1104

    摘要： Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.

    摘要翻译： 公开了一种具有高抗α射线诱导的软错误免疫力的静态型记忆体。 存储单元在两个数据存储节点1和2之间具有耦合电容Cc。其中形成驱动器MOS晶体管MN3，MN4和传输MOS晶体管MN1，MN2的p阱（或p衬底）连接到 一个Vbb发生器。 电压Vbb被设定为低于存储单元信号电位的低电平VL。 即使当低电压侧节点2的电位变化量DELTA VL大时，存在于与MN1-MN4的源极或漏极对应的n型扩散层与p阱（或p-衬底）之间的寄生二极管， 不打开 因此可以防止错误的操作。