公开(公告)号：US6140711A

公开(公告)日：2000-10-31

申请号：US108969

申请日：1998-07-02

申请人： Satoshi Machida ,  Akiyuki Minami

发明人： Satoshi Machida ,  Akiyuki Minami

IPC分类号： H01L21/027 ,  H01L23/544

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/12044

摘要： An alignment mark which is employed for the alignment of a semiconductor substrate during a lithography process in the production of a semiconductor element, includes a trough-like pattern having a width roughly equal to the width of a circuit element provided at the surface of the semiconductor substrate. Since the width of the trough-like pattern is set roughly equal to that of the circuit element, a secure trough-like pattern that will not be removed to an excessive degree during processes such as etch-back is formed at the surface of the semiconductor substrate, even if the alignment mark is formed concurrently with the formation of the circuit element. Consequently, a clear alignment mark that can be produced concurrently with the formation of a circuit element of the semiconductor circuit element and that presents no risk of collapsing or separating, is provided.

摘要翻译： 在制造半导体元件的光刻工艺期间用于半导体衬底的对准的对准标记包括具有与设置在半导体表面处的电路元件的宽度大致相等的宽度的槽状图案 基质。 由于槽状图案的宽度大致等于电路元件的宽度，因此在半导体的表面形成了不会在诸如回蚀的工艺中过度去除的牢固的槽状图案 基板，即使对准标记与电路元件的形成同时形成。 因此，提供了可以与半导体电路元件的电路元件的形成同时产生并且不存在塌陷或分离的风险的清晰的对准标记。

公开(公告)号：US06601314B2

公开(公告)日：2003-08-05

申请号：US10034108

申请日：2002-01-03

申请人： Satoshi Machida ,  Akiyuki Minami

发明人： Satoshi Machida ,  Akiyuki Minami

IPC分类号： G01D2100

CPC分类号： H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for manufacturing a highly reliable alignment mark in which by-products do not form at an aligning mark position during patterning. In this method, an intermediate layer is disposed on an upper layer of a first wiring to protect the first wiring. Then, a filling material is coated thereon to fill in a through hole. Thereafter, a plug is formed by etch-backing, and a second wiring is formed.

公开(公告)号：US06562188B2

公开(公告)日：2003-05-13

申请号：US10196413

申请日：2002-07-17

申请人： Akiyuki Minami ,  Satoshi Machida

发明人： Akiyuki Minami ,  Satoshi Machida

IPC分类号： H01L2100

CPC分类号： G03F7/70633 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

公开(公告)号：US06440262B1

公开(公告)日：2002-08-27

申请号：US10061285

申请日：2002-02-04

申请人： Akiyuki Minami ,  Satoshi Machida

发明人： Akiyuki Minami ,  Satoshi Machida

IPC分类号： H01L2100

CPC分类号： G03F7/70633 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

摘要翻译： 用于测量设置在半导体晶片上的光掩模的覆盖精度的抗蚀剂标记包括形成在基板上的第一开口的第一测量标记，在第一测量标记和第一开口中形成的中间层，框架 形成在中间层上的第二测量标记，以及形成在中间层上的与第二测量标记间隔开的第三测量标记。 第二测量标记的宽度足够短，不受热流现象引起的变形的影响。

公开(公告)号：US06368980B1

公开(公告)日：2002-04-09

申请号：US09458819

申请日：1999-12-13

申请人： Akiyuki Minami ,  Satoshi Machida

发明人： Akiyuki Minami ,  Satoshi Machida

IPC分类号： H01L2100

CPC分类号： G03F7/70633 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

摘要翻译： 用于测量设置在半导体晶片上的光掩模的覆盖精度的抗蚀剂标记包括形成在基板上的第一开口的第一测量标记，在第一测量标记和第一开口中形成的中间层，框架 形成在中间层上的第二测量标记，以及形成在中间层上的与第二测量标记间隔开的第三测量标记。 第二测量标记的宽度足够短，不受热流现象引起的变形的影响。

公开(公告)号：US06589385B2

公开(公告)日：2003-07-08

申请号：US10196379

申请日：2002-07-17

申请人： Akiyuki Minami ,  Satoshi Machida

发明人： Akiyuki Minami ,  Satoshi Machida

IPC分类号： H01L2100

CPC分类号： G03F7/70633 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

公开(公告)号：US06559063B2

公开(公告)日：2003-05-06

申请号：US10061332

申请日：2002-02-04

申请人： Akiyuki Minami ,  Satoshi Machida

发明人： Akiyuki Minami ,  Satoshi Machida

IPC分类号： H01L2100

CPC分类号： G03F7/70633 ,  H01L22/34 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.

公开(公告)号：US07804127B2

公开(公告)日：2010-09-28

申请号：US12155983

申请日：2008-06-12

申请人： Koji Takaya ,  Akiyuki Minami

发明人： Koji Takaya ,  Akiyuki Minami

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7923

摘要： A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.

摘要翻译： 半导体非易失性存储单元包括具有包含具有脊部分的激活区域的含Si（硅）层的衬底; 嵌入激活区域的两侧的元件分离区域; 在所述脊部上形成有栅极绝缘膜的栅电极，用于覆盖所述脊部的两个侧面的一部分和所述元件分离区域的上表面; 形成在所述脊部的表层区域中的沟道形成区域; 在纵向方向上形成在通道形成区域的两侧的延伸区域; 以及能够积聚电荷的电荷积累层和形成在所述延伸区域上的侧壁以及在所述栅极电极的侧表面中的一个或两个在所述纵向方向上彼此面对的电荷累积层。

公开(公告)号：US20090045454A1

公开(公告)日：2009-02-19

申请号：US12155983

申请日：2008-06-12

申请人： Koji Takaya ,  Akiyuki Minami

发明人： Koji Takaya ,  Akiyuki Minami

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11568 ,  H01L29/42352 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7923

摘要： A semiconductor non-volatile memory cell includes an Si (silicon) layer containing substrate including an activation region having a ridge portion; an element separation region embedded in both sides of the activation region; a gate electrode with a gate insulation film inbetween formed over the ridge portion for covering a part of both side surfaces of the ridge portion and an upper surface of the element separation region; a channel forming region formed in a surface layer region of the ridge portion; an extension region formed on both sides of the channel forming region in the longitudinal direction; and an electric charge accumulation layer capable of accumulating electric charges and a sidewall formed on the extension region and one or both of side surfaces of the gate electrode facing with each other in the longitudinal direction.

摘要翻译： 半导体非易失性存储单元包括具有包含具有脊部分的激活区域的含Si（硅）层的衬底; 嵌入激活区域的两侧的元件分离区域; 在所述脊部上形成有栅极绝缘膜的栅电极，用于覆盖所述脊部的两个侧面的一部分和所述元件分离区域的上表面; 形成在所述脊部的表层区域中的沟道形成区域; 在纵向方向上形成在通道形成区域的两侧的延伸区域; 以及能够积聚电荷的电荷积累层和形成在所述延伸区域上的侧壁以及在所述栅极电极的侧表面中的一个或两个在所述纵向方向上彼此面对的电荷累积层。

公开(公告)号：US06757049B2

公开(公告)日：2004-06-29

申请号：US10259606

申请日：2002-09-30

申请人： Akiyuki Minami

发明人： Akiyuki Minami

IPC分类号： G03B2768

CPC分类号： G03F9/7046 ,  G03F7/70258 ,  G03F7/70425 ,  G03F7/70875

摘要： In order to reduce a displacement in position between an under pattern and a resist pattern due to distortion, a reticle (18) formed with reticle alignment marks (32) at at least two points is used, reticle microscopes (34) are respectively placed in association with positions of the reticle alignment marks (32) at the time that the reticle (18) is supported by a reticle stage (20) and rotated about an optical axis (Z axis) of an image-forming optical system (26) by 90°, and the reticle alignment marks (32) are detected by any reticle microscope (34) even if the reticle (18) being supported by the reticle stage (20) is rotated about the Z axis.

摘要翻译： 为了减少由于变形引起的下模式和抗蚀剂图案之间的位置偏移，使用在至少两点形成有标线片对准标记（32）的掩模版（18），将掩模版显微镜（34）分别放置在 与标线片对准标记（32）的位置相关联，在标线片（18）由标线片平台（20）支撑并且绕图像形成光学系统（26）的光轴（Z轴）旋转时，通过 90°，并且即使由标线片台（20）支撑的标线片（18）围绕Z轴旋转，也可通过任何掩模版显微镜（34）检测标线片对准标记（32）。