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    Level shift circuit
    1.
    发明授权
    Level shift circuit 有权
    电平移位电路

    公开(公告)号：US07639060B2

    公开(公告)日：2009-12-29

    申请号：US12076521

    申请日：2008-03-19

    申请人： Satoshi Shiraki ,  Hiroyuki Ban ,  Junichi Nagata

    发明人： Satoshi Shiraki ,  Hiroyuki Ban ,  Junichi Nagata

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018571 ,  H01L27/0251 ,  H03K5/003 ,  H03K19/00361

    摘要： A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.

    摘要翻译： 电平移位电路包括：第一电容器电路，包括串联连接在接地和预定电位之间的电容器;耦合到第一电容器电路的预定电位侧的第一触发电路;耦合到第一电容器的接地侧的输入端子 电路，包括串联连接在接地和预定电位之间的电容器的第二电容器电路，耦合到第二电容器电路的预定电位侧的第二触发电路，耦合在第二电容器的输入端子和地电位侧之间的反相器 电容器电路和SR锁存电路，其具有耦合到第一触发电路的输出的第一输入和耦合到第二触发电路的输出的第二输入。

    Level shift circuit
    2.
    发明申请
    Level shift circuit 有权
    电平移位电路

    公开(公告)号：US20080231340A1

    公开(公告)日：2008-09-25

    申请号：US12076521

    申请日：2008-03-19

    申请人： Satoshi Shiraki ,  Hiroyuki Ban ,  Junichi Nagata

    发明人： Satoshi Shiraki ,  Hiroyuki Ban ,  Junichi Nagata

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018571 ,  H01L27/0251 ,  H03K5/003 ,  H03K19/00361

    摘要： A level shift circuit includes a first capacitor circuit including capacitors connected in series between a ground and a predetermined potential, a first trigger circuit coupled to the predetermined potential side of the first capacitor circuit, an input terminal coupled to the ground side of the first capacitor circuit, a second capacitor circuit including capacitors connected in series between the ground and the predetermined potential, a second trigger circuit coupled to the predetermined potential side of the second capacitor circuit, an inverter coupled between the input terminal and the ground potential side of the second capacitor circuit, and a SR latch circuit having a first input coupled to an output of the first trigger circuit and a second input coupled to an output of the second trigger circuit.

    摘要翻译： 电平移位电路包括：第一电容器电路，包括串联连接在接地和预定电位之间的电容器;耦合到第一电容器电路的预定电位侧的第一触发电路;耦合到第一电容器的接地侧的输入端子 电路，包括串联连接在接地和预定电位之间的电容器的第二电容器电路，耦合到第二电容器电路的预定电位侧的第二触发电路，耦合在第二电容器的输入端子和地电位侧之间的反相器 电容器电路和SR锁存电路，其具有耦合到第一触发电路的输出的第一输入和耦合到第二触发电路的输出的第二输入。

    Semiconductor device and method for manufacturing the same
    5.
    发明申请
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US20090127605A1

    公开(公告)日：2009-05-21

    申请号：US12010111

    申请日：2008-01-22

    申请人： Satoshi Shiraki ,  Hiroyuki Ban ,  Akira Yamada

    发明人： Satoshi Shiraki ,  Hiroyuki Ban ,  Akira Yamada

    IPC分类号： H01L29/66 ,  H01L21/66

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled.

    摘要翻译： 半导体器件包括：n个晶体管元件; n电阻元件; 和n个电容元件，每种元件串联在第一和第二端子之间。 每个晶体管元件的栅极具有栅极焊盘，并且每个晶体管元件包括设置在两侧的晶体管焊盘。 每个电阻元件包括设置在两侧的电阻垫。 每个电容元件包括设置在两侧的电容焊盘。 除了第一级晶体管元件之外的栅极焊盘，对应的电阻焊盘和对应的电容焊盘是电耦合的。 第一级中的一个晶体管焊盘，一个电阻焊盘和一个电容焊盘电耦合。 第n级中的一个晶体管焊盘，一个电阻焊盘和一个电容焊盘电耦合。

    Semiconductor device having bipolar transistors
    6.
    发明授权
    Semiconductor device having bipolar transistors 失效
    具有双极晶体管的半导体器件

    公开(公告)号：US06768183B2

    公开(公告)日：2004-07-27

    申请号：US10125582

    申请日：2002-04-19

    申请人： Shigeki Takahashi ,  Satoshi Shiraki ,  Hiroaki Himi ,  Hiroyuki Ban ,  Osamu Seya

    发明人： Shigeki Takahashi ,  Satoshi Shiraki ,  Hiroaki Himi ,  Hiroyuki Ban ,  Osamu Seya

    IPC分类号： H01L2900

    CPC分类号： H01L27/0826 ,  H01L27/0623

    摘要： An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.

    摘要翻译： 在半导体衬底中形成NPN双极晶体管和PNP双极晶体管。 NPN双极晶体管具有p型发射极区域，p型集电极区域和n型基极区域，并且形成在NPN形成区域中。 PNP双极晶体管具有n型发射极区域，n型集电极区域和p型基极区域，并且形成在PNP形成区域中。 在NPN形成区域和PNP形成区域的至少一个中仅形成一个导电型掩埋区域。 从p型发射极区域流向n型基极区域的电流在与基板垂直的方向上流入n型基极区域。

    Semiconductor device and method for manufacturing the same
    7.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07821069B2

    公开(公告)日：2010-10-26

    申请号：US12010111

    申请日：2008-01-22

    申请人： Satoshi Shiraki ,  Hiroyuki Ban ,  Akira Yamada

    发明人： Satoshi Shiraki ,  Hiroyuki Ban ,  Akira Yamada

    IPC分类号： H01L23/62

    CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled.

    摘要翻译： 半导体器件包括：n个晶体管元件; n电阻元件; 和n个电容元件，每种元件串联在第一和第二端子之间。 每个晶体管元件的栅极具有栅极焊盘，并且每个晶体管元件包括设置在两侧的晶体管焊盘。 每个电阻元件包括设置在两侧的电阻垫。 每个电容元件包括设置在两侧的电容焊盘。 除了第一级晶体管元件之外的栅极焊盘，对应的电阻焊盘和对应的电容焊盘是电耦合的。 第一级中的一个晶体管焊盘，一个电阻焊盘和一个电容焊盘电耦合。 第n级中的一个晶体管焊盘，一个电阻焊盘和一个电容焊盘电耦合。

    Constant voltage circuit with a substitute circuit in case of input voltage lowering
    10.
    发明授权
    Constant voltage circuit with a substitute circuit in case of input voltage lowering 有权
    在输入电压降低的情况下，带有替代电路的恒压电路

    公开(公告)号：US06465996B2

    公开(公告)日：2002-10-15

    申请号：US09799106

    申请日：2001-03-06

    申请人： Junichi Nagata ,  Kiyoshi Yamamoto ,  Hirokazu Itakura ,  Masahiro Kitagawa ,  Hiroyuki Ban ,  Hiroyuki Kawabata ,  Shinichi Maeda

    发明人： Junichi Nagata ,  Kiyoshi Yamamoto ,  Hirokazu Itakura ,  Masahiro Kitagawa ,  Hiroyuki Ban ,  Hiroyuki Kawabata ,  Shinichi Maeda

    IPC分类号： G05F316

    CPC分类号： H02J7/0063

    摘要： A constant voltage circuit robust to the input voltage lowering is disclosed. The invention is applied to a constant voltage circuit fed with an input voltage through first and second power conductors for transferring the input voltage to a load as an output voltage through an output transistor. An inventive constant voltage circuit is provided with a substitute circuit, responsive to a detection of the lowing of the input voltage to a predetermined voltage, for providing a substitute output path that is connected in parallel with the output transistor. Doing this minimize the degree of lowering of the second voltage due to the lowering of said first voltage. The output transistor may be nay of NPN and PNP transistors and P-type and N-type MOS FETs.

    摘要翻译： 公开了对输入电压降低稳健的恒定电压电路。 本发明应用于通过第一和第二电力导体馈送输入电压的恒压电路，用于通过输出晶体管将输入电压传送到负载作为输出电压。 本发明的恒压电路具有替代电路，响应于将输入电压降低到预定电压，以提供与输出晶体管并联连接的替代输出路径。 这样做使得由于所述第一电压的降低而使第二电压降低的程度最小化。 输出晶体管可以是NPN和PNP晶体管以及P型和N型MOS FET。