公开(公告)号：US20230080635A1

公开(公告)日：2023-03-16

申请号：US17950952

申请日：2022-09-22

Applicant: Schottky LSI, Inc.

Inventor： Pierre Dermy

IPC: H01L29/872 ,  H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/78

Abstract: This application is directed to integrating a field-effect transistor (FinFET) and a Schottky barrier diode on a substrate. A first fin structure and a second fin structure are formed on the substrate. The first fin structure includes a channel portion extending to two stressor portions on two opposite sides of the channel portion, and the second fin structure includes a junction portion. A source structure and a drain structure of the FinFET are formed on the two stressor portions of the first fin structure, respectively. A source metallic material, a drain metallic material, a first metallic material are formed to electrically couple to the source structure, the drain structure, and the junction portion of the second fin structure, respectively, thereby providing a Schottky junction between the junction portion of the second fin structure and the first metallic material.

公开(公告)号：US20200287546A1

公开(公告)日：2020-09-10

申请号：US16883753

申请日：2020-05-26

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/0956 ,  H03K19/0948 ,  H03K19/017 ,  H01L27/11546 ,  H01L27/118 ,  H01L31/0376 ,  H03K19/17728 ,  H01L25/065 ,  H01L31/032 ,  H01L27/112 ,  H01L27/105 ,  H01L27/108 ,  H01L31/074 ,  H01L27/02 ,  H01L27/11526 ,  H01L31/072 ,  H01L49/02

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

公开(公告)号：US20180212605A1

公开(公告)日：2018-07-26

申请号：US15817026

申请日：2017-11-17

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/0956 ,  H03K19/0948 ,  H03K19/017

CPC classification number: H03K19/0956 ,  H01L25/065 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/11286 ,  H01L27/11293 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L28/00 ,  H01L28/20 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H01L2924/0002 ,  H03K19/01707 ,  H03K19/0948 ,  H03K19/17728 ,  Y02E10/50 ,  H01L2924/00

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

公开(公告)号：US11870438B2

公开(公告)日：2024-01-09

申请号：US17752673

申请日：2022-05-24

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/09 ,  H03K19/0956 ,  H01L25/065 ,  H01L27/02 ,  H01L27/105 ,  H01L27/118 ,  H01L49/02 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/017 ,  H03K19/0948 ,  H03K19/17728 ,  H10B12/00 ,  H10B20/00 ,  H10B41/40 ,  H10B41/49

CPC classification number: H03K19/0956 ,  H01L25/065 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11807 ,  H01L28/00 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/01707 ,  H03K19/0948 ,  H03K19/17728 ,  H10B12/50 ,  H10B20/00 ,  H10B20/38 ,  H10B20/60 ,  H10B20/65 ,  H10B41/40 ,  H10B41/49 ,  H01L28/20 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

公开(公告)号：US11342916B2

公开(公告)日：2022-05-24

申请号：US16883753

申请日：2020-05-26

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/09 ,  H03K19/0956 ,  H03K19/0948 ,  H03K19/017 ,  H01L27/11546 ,  H01L27/118 ,  H01L31/0376 ,  H03K19/17728 ,  H01L25/065 ,  H01L31/032 ,  H01L27/112 ,  H01L27/105 ,  H01L27/108 ,  H01L31/074 ,  H01L27/02 ,  H01L27/11526 ,  H01L31/072 ,  H01L49/02

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

公开(公告)号：US10666260B2

公开(公告)日：2020-05-26

申请号：US15817026

申请日：2017-11-17

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/0956 ,  H03K19/0948 ,  H03K19/017 ,  H01L27/11546 ,  H01L27/118 ,  H01L31/0376 ,  H03K19/17728 ,  H01L25/065 ,  H01L31/032 ,  H01L27/112 ,  H01L27/105 ,  H01L27/108 ,  H01L31/074 ,  H01L27/02 ,  H01L27/11526 ,  H01L31/072 ,  H01L49/02

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

公开(公告)号：US20240120922A1

公开(公告)日：2024-04-11

申请号：US18544309

申请日：2023-12-18

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/0956 ,  H01L25/065 ,  H01L27/02 ,  H01L27/105 ,  H01L27/118 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/017 ,  H03K19/0948 ,  H03K19/17728 ,  H10B12/00 ,  H10B20/00 ,  H10B41/40 ,  H10B41/49

CPC classification number: H03K19/0956 ,  H01L25/065 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11807 ,  H01L28/00 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/01707 ,  H03K19/0948 ,  H03K19/17728 ,  H10B12/50 ,  H10B20/00 ,  H10B20/38 ,  H10B20/60 ,  H10B20/65 ,  H10B41/40 ,  H10B41/49 ,  H01L28/20 ,  H01L2924/0002 ,  Y02E10/50

Abstract: Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output is coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

公开(公告)号：US20220286134A1

公开(公告)日：2022-09-08

申请号：US17752673

申请日：2022-05-24

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/0956 ,  H01L25/065 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/118 ,  H01L49/02 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/017 ,  H03K19/0948 ,  H03K19/17728

Abstract: Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

公开(公告)号：US09853643B2

公开(公告)日：2017-12-26

申请号：US15484040

申请日：2017-04-10

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/0185 ,  H03K19/0948 ,  H03K19/0956 ,  H03K19/017

CPC classification number: H03K19/0956 ,  H01L21/8238 ,  H01L25/065 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/11286 ,  H01L27/11293 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L28/00 ,  H01L28/20 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H01L2924/0002 ,  H03K19/01707 ,  H03K19/0948 ,  H03K19/17728 ,  Y02E10/50 ,  H01L2924/00

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

公开(公告)号：US20170287891A1

公开(公告)日：2017-10-05

申请号：US15484040

申请日：2017-04-10

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H01L27/02 ,  H01L27/105 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/07 ,  H01L27/108

CPC classification number: H03K19/0956 ,  H01L21/8238 ,  H01L25/065 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/11286 ,  H01L27/11293 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11807 ,  H01L28/00 ,  H01L28/20 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H01L2924/0002 ,  H03K19/01707 ,  H03K19/0948 ,  H03K19/17728 ,  Y02E10/50 ,  H01L2924/00

Abstract: Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.