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    Fully silicided field effect transistors
    5.
    发明授权
    Fully silicided field effect transistors 有权
    全硅化场效应晶体管

    公开(公告)号：US07220662B2

    公开(公告)日：2007-05-22

    申请号：US10905549

    申请日：2005-01-10

    申请人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

    发明人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66545

    摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.

    摘要翻译： 通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

    FULLY SILICIDED FIELD EFFECT TRANSISTORS
    6.
    发明申请
    FULLY SILICIDED FIELD EFFECT TRANSISTORS 有权
    全硅氧化物场效应晶体管

    公开(公告)号：US20060154461A1

    公开(公告)日：2006-07-13

    申请号：US10905549

    申请日：2005-01-10

    申请人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

    发明人： Huilong Zhu ,  Sunfei Fang ,  Zhijiong Luo

    IPC分类号： H01L21/4763 ,  H01L21/3205

    CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/66545

    摘要： Fully silicided planar field effect transistors are formed by avoiding the conventional chemical-mechanical polishing step to expose the silicon gate by etching the sidewalls down to the silicon; depositing a sacrificial oxide layer thinner on the top of gate and sidewall of spacers, but thicker over the S/D areas, etching the oxide to expose the top of stacked gate while protecting the S/D; recessing the silicon; stripping the oxide; depositing metal and annealing to form silicide over the gate and S/D.

    摘要翻译： 通过避免常规的化学机械抛光步骤通过将侧壁蚀刻到硅来暴露硅栅来形成全硅化平面场效应晶体管; 在间隔物的栅极和侧壁的顶部上沉积牺牲氧化物层，但在S / D区域上较厚，在保护S / D的同时蚀刻氧化物以露出堆叠栅极的顶部; 凹陷硅; 剥离氧化物; 沉积金属和退火以在栅极和S / D上形成硅化物。

    METHOD AND STRUCTURE TO FORM SELF-ALIGNED SELECTIVE-SOI
    7.
    发明申请
    METHOD AND STRUCTURE TO FORM SELF-ALIGNED SELECTIVE-SOI 失效
    形成自对准选择性SOI的方法和结构

    公开(公告)号：US20070278591A1

    公开(公告)日：2007-12-06

    申请号：US11421594

    申请日：2006-06-01

    申请人： Zhijiong Luo ,  Yung Chong ,  Kevin Dezfulian ,  Huilong Zhu ,  Judson Holt

    发明人： Zhijiong Luo ,  Yung Chong ,  Kevin Dezfulian ,  Huilong Zhu ,  Judson Holt

    IPC分类号： H01L29/76 ,  H01L21/8238

    CPC分类号： H01L29/66628 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

    摘要： Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

    摘要翻译： 公开了形成自对准选择性半导体绝缘体（SOI）结构和相关结构的方法。 在一个实施例中，一种方法包括提供基底; 在所述衬底内的沟道上形成栅极结构; 使靠近通道的衬底的一部分凹陷; 在所述凹部的底部形成绝缘层; 以及在绝缘层上方形成半导体材料。 半导体材料的上表面可以是倾斜的。 MOSFET结构可以包括衬底; 一个渠道 与沟道相邻的源极区域和漏极区域; 在通道和衬底上方的栅极结构; 远离栅极结构的浅沟槽隔离（STI）; 在源极区域和漏极区域中的至少一个中选择性地铺设绝缘层; 以及在选择性铺设的绝缘层上方的外延生长的半导体材料。

    Field effect transistors (FETs) with multiple and/or staircase silicide
    8.
    发明授权
    Field effect transistors (FETs) with multiple and/or staircase silicide 有权
    具有多个和/或阶梯硅化物的场效应晶体管（FET）

    公开(公告)号：US07816219B2

    公开(公告)日：2010-10-19

    申请号：US11850076

    申请日：2007-09-05

    申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

    发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

    摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

    摘要翻译： 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

    FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE
    9.
    发明申请
    FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 有权
    具有多个和/或多个硅化物的场效应晶体管（FET）

    公开(公告)号：US20070298572A1

    公开(公告)日：2007-12-27

    申请号：US11850076

    申请日：2007-09-05

    申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

    发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

    摘要： A semiconductor structure and method for forming the same. First, a semiconductor structure is provided, including (a) a semiconductor layer including (i) a channel region and (ii) first and second source/drain (S/D) extension regions, and (iii) first and second S/D regions, (b) a gate dielectric region in direction physical contact with the channel region via a first interfacing surface that defines a reference direction essentially perpendicular to the first interfacing surface, and (c) a gate region in direct physical contact with the gate dielectric region, wherein the gate dielectric region is sandwiched between and electrically insulates the gate region and the channel region. Then, (i) a first shallow contact region is formed in direct physical contact with the first S/D extension region, and (ii) a first deep contact region is formed in direct physical contact with the first S/D region and the first shallow contact region.

    摘要翻译： 一种半导体结构及其形成方法。 首先，提供半导体结构，其包括（a）包括（i）沟道区和（ii）第一和第二源/漏（S / D）延伸区的半导体层，以及（iii）第一和第二S / D 区域，（b）通过限定基本上垂直于第一接口表面的参考方向的第一接口表面方向与沟道区域物理接触的栅极电介质区域，以及（c）与栅极电介质直接物理接触的栅极区域 区域，其中栅极电介质区域夹在栅极区域和沟道区域之间并使电绝缘。 然后，（i）第一浅接触区域形成为与第一S / D延伸区域直接物理接触，并且（ii）第一深接触区域形成为与第一S / D区域和第一浅/ 浅接触区域。

    FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE
    10.
    发明申请
    FIELD EFFECT TRANSISTORS (FETs) WITH MULTIPLE AND/OR STAIRCASE SILICIDE 失效
    具有多个和/或多个硅化物的场效应晶体管（FET）

    公开(公告)号：US20060244075A1

    公开(公告)日：2006-11-02

    申请号：US10908087

    申请日：2005-04-27

    申请人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

    发明人： Xiangdong Chen ,  Sunfei Fang ,  Zhijiong Luo ,  Haining Yang ,  Huilong Zhu

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7833 ,  H01L29/665 ,  H01L29/6659

    摘要： A semiconductor structure and method for forming the same. The semiconductor structure comprises a field effect transistor (FET) having a channel region disposed between first and second source/drain (S/D) extension regions which are in turn in direct physical contact with first and second S/D regions, respective. First and second silicide regions are formed such that the first silicide region is in direct physical contact with the first S/D region and the first S/D extension region, whereas the second silicide region is in direct physical contact with the second S/D region and the second S/D extension region. The first silicide region is thinner for regions in contact with first S/D extension region than for regions in contact with the first S/D region. Similarly, the second silicide region is thinner for regions in contact with second S/D extension region than for regions in contact with the second S/D region.

    摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括场效应晶体管（FET），其具有设置在第一和第二源极/漏极（S / D）延伸区域之间的沟道区域，第一和第二源极/漏极（S / D）延伸区域又分别与第一和第二S / D区域直接物理接触。 形成第一和第二硅化物区域，使得第一硅化物区域与第一S / D区域和第一S / D延伸区域直接物理接触，而第二硅化物区域与第二S / D区域直接物理接触 区域和第二S / D扩展区域。 对于与第一S / D延伸区域接触的区域，第一硅化物区域比与第一S / D区域接触的区域更薄。 类似地，对于与第二S / D延伸区域接触的区域，第二硅化物区域比与第二S / D区域接触的区域更薄。