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1.发明申请OPTO-THERMAL ANNEALING METHODS FOR FORMING METAL GATE AND FULLY SILICIDED GATE-FIELD EFFECT TRANSISTORS 有权用于形成金属门和完全硅化的栅极效应晶体管的光热退火方法公开(公告)号：US20080220581A1
公开(公告)日：2008-09-11
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。
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2.发明授权Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法公开(公告)号：US07410852B2
公开(公告)日：2008-08-12
申请号：US11408522
申请日：2006-04-21
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/8234 , H01L21/42
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。
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3.发明授权Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors 有权用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法公开(公告)号：US08039331B2
公开(公告)日：2011-10-18
申请号：US12120286
申请日：2008-05-14
申请人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
发明人： Scott D. Allen , Cyril Cabral, Jr. , Kevin K. Dezfulian , Sunfei Fang , Brian J. Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement H. Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。
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4.发明申请Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors 有权用于形成金属栅极和全硅化栅场效应晶体管的光热退火方法公开(公告)号：US20070249131A1
公开(公告)日：2007-10-25
申请号：US11408522
申请日：2006-04-21
申请人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
发明人： Scott Allen , Cyril Cabral , Kevin Dezfulian , Sunfei Fang , Brian Greene , Rajarao Jammy , Christian Lavoie , Zhijiong Luo , Hung Ng , Chun-Yung Sung , Clement Wann , Huilong Zhu
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L21/268 , H01L21/2686 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/28176 , H01L21/324 , H01L29/517 , H01L29/665
摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.
摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。
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5.发明授权Formation of fully silicided metal gate using dual self-aligned silicide process 失效使用双自对准硅化物工艺形成完全硅化金属栅极公开(公告)号：US07785999B2
公开(公告)日：2010-08-31
申请号：US11830277
申请日：2007-07-30
申请人： Cyril Cabral, Jr. , Chester T. Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam G. Shahidi , Michelle L. Steen , Clement H. Wann
发明人： Cyril Cabral, Jr. , Chester T. Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam G. Shahidi , Michelle L. Steen , Clement H. Wann
IPC分类号： H01L21/44 , H01L21/8242
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。
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6.发明授权Formation of fully silicided metal gate using dual self-aligned silicide process 失效使用双自对准硅化物工艺形成完全硅化金属栅极公开(公告)号：US07271455B2
公开(公告)日：2007-09-18
申请号：US10890753
申请日：2004-07-14
申请人： Cyril Cabral, Jr. , Chester T. Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam G. Shahidi , Michelle L. Steen , Clement H. Wann
发明人： Cyril Cabral, Jr. , Chester T. Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam G. Shahidi , Michelle L. Steen , Clement H. Wann
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。
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7.发明申请FORMATION OF FULLY SILICIDED METAL GATE USING DUAL SELF-ALIGNED SILICIDE PROCESS 失效使用双自对准硅胶工艺形成全硅酸金属门公开(公告)号：US20080026551A1
公开(公告)日：2008-01-31
申请号：US11830277
申请日：2007-07-30
申请人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
发明人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
IPC分类号： H01L21/3205
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译： 提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。
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8.发明申请Formation of fully silicided metal gate using dual self-aligned silicide process 失效使用双自对准硅化物工艺形成完全硅化金属栅极公开(公告)号：US20060022280A1
公开(公告)日：2006-02-02
申请号：US10890753
申请日：2004-07-14
申请人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
发明人： Cyril Cabral , Chester Dziobkowski , Sunfei Fang , Evgeni Gousev , Rajarao Jammy , Vijay Narayanan , Vamsi Paruchuri , Ghavam Shahidi , Michelle Steen , Clement Wann
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： H01L29/66507 , H01L21/28097 , H01L21/823443 , H01L29/66545
摘要： An advanced gate structure that includes a fully silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.
摘要翻译： 提供了一种先进的栅极结构，其包括完全硅化金属栅极和硅化物源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。
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9.发明授权Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectrics 有权在具有高k电介质的CMOS器件制造中实现势垒层的选择性实现以实现阈值电压控制公开(公告)号：US08193051B2
公开(公告)日：2012-06-05
申请号：US13047172
申请日：2011-03-14
申请人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
发明人： Nestor A. Bojarczuk, Jr. , Cyril Cabral, Jr. , Eduard A. Cartier , Matthew W. Copel , Martin M. Frank , Evgeni P. Gousev , Supratik Guha , Rajarao Jammy , Vijay Narayanan , Vamsi K. Paruchuri
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/823857 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.
摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。
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公开(公告)号：US07667278B2
公开(公告)日：2010-02-23
申请号：US11372140
申请日：2006-03-10
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L29/06 , H01L29/12
CPC分类号： H01L29/4966 , H01L21/823842
摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.
摘要翻译： 提供了包括包括包括金属碳化物的栅电极和至少一种制造方法的至少一个FET的互补金属氧化物半导体（CMOS）的半导体器件。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。
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