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    Dielectric interconnect structures and methods for forming the same
    7.
    发明申请
    Dielectric interconnect structures and methods for forming the same 有权
    介电互连结构及其形成方法

    公开(公告)号：US20070224801A1

    公开(公告)日：2007-09-27

    申请号：US11390390

    申请日：2006-03-27

    申请人： Chih-Chao Yang ,  Louis Hsu ,  Rajiv Joshi

    发明人： Chih-Chao Yang ,  Louis Hsu ,  Rajiv Joshi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

    摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

    摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施例中，通过用气体离子等离子体（例如，Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

    Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability
    8.
    发明申请
    Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability 失效
    用于评估静态存储单元动态稳定性的内部非对称方法和电路

    公开(公告)号：US20070058466A1

    公开(公告)日：2007-03-15

    申请号：US11225652

    申请日：2005-09-13

    申请人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

    发明人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

    IPC分类号： G11C29/00

    CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

    摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

    摘要翻译： 用于评估静态存储单元动态稳定性的内部非对称方法和电路为提高存储器阵列的性能提供了超越现有水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

    Electronic circuit having variable biasing
    9.
    发明申请
    Electronic circuit having variable biasing 失效
    具有可变偏置的电子电路

    公开(公告)号：US20070018257A1

    公开(公告)日：2007-01-25

    申请号：US11184698

    申请日：2005-07-19

    申请人： Rajiv Joshi

    发明人： Rajiv Joshi

    IPC分类号： H01L29/76

    CPC分类号： G11C11/413 ,  G11C7/1051 ,  G11C7/1078

    摘要： Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a substrate and another type formed on the wells. For example, the circuit can be a memory circuit, and the selective well bias can be changed depending on whether a READ or WRITE operation is being conducted. In another aspect, cells in a memory circuit can be subjected to variable bias depending on conditions, such as, again, whether a READ or WRITE operation is underway.

    摘要翻译： 提供了用于选择性地偏置诸如互补金属氧化物半导体（CMOS）电路的电路中的阱的技术，其具有两种类型的晶体管，一种类型形成在衬底上，另一种类型形成在阱上。 例如，电路可以是存储器电路，并且可以根据是否正在进行READ或WRITE操作来改变选择阱偏置。 在另一方面，存储器电路中的单元可以根据诸如再次READ或WRITE操作正在进行的条件经受可变偏置。

    SINGLE SUPPLY LEVEL CONVERTER
    10.
    发明申请
    SINGLE SUPPLY LEVEL CONVERTER 有权
    单电源电平转换器

    公开(公告)号：US20060279334A1

    公开(公告)日：2006-12-14

    申请号：US11466754

    申请日：2006-08-23

    申请人： Anthony Correale ,  Rajiv Joshi ,  David Kung ,  Zhigang Pan ,  Ruchir Puri

    发明人： Anthony Correale ,  Rajiv Joshi ,  David Kung ,  Zhigang Pan ,  Ruchir Puri

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018521 ,  H03K19/0948

    摘要： A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

    摘要翻译： 用于连接由不同电源电压提供的两个电路的电平转换器，以及包括在两个不同电压岛中的电平转换器接口电路的集成电路。 第一缓冲器由虚拟电源提供，并从低电压电路接收输入信号。 第一个缓冲器驱动第二个缓冲器，该缓冲器由较高的电源电压供电。 来自第二缓冲器的输出切换电源选择以选择性地将较高电源电压或降低的电源电压传递到第一缓冲器。