公开(公告)号：US08248123B2

公开(公告)日：2012-08-21

申请号：US12608788

申请日：2009-10-29

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： H03L7/06 ,  H03K5/00

CPC分类号： H03L7/093

摘要： A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node, such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

摘要翻译： 一种环路滤波器，具有在其上接收到环路滤波器的输入信号的第一节点，在其上提供环路滤波器的输出信号的第二节点以及至少产生零的第一电路的级联布置， 产生第一极的第二电路和产生第二极以形成至少三阶的无源环路滤波器的第三电路。 级联装置包括将第一节点耦合到第二节点的第一信号路径，使得第一电路通过第二电路和第三电路耦合到第一节点。 此外，环路滤波器包括至少一个晶体管电路和在第一节点并联耦合到第一信号路径的第二信号路径，并通过晶体管电路耦合到第二节点。

公开(公告)号：US07911241B1

公开(公告)日：2011-03-22

申请号：US12608522

申请日：2009-10-29

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： H03B21/00

CPC分类号： H03L7/1976

摘要： A frequency synthesizer circuit that reduces undesired spurious sidebands while maintaining phase noise performance having a phase locked loop circuit comprising at least a phase detector, a controlled oscillator, a frequency divider coupled to the controlled oscillator for adjusting a frequency division of the frequency divider in response to a received control signal generated from a divisor value, a dithering circuit for providing a dither signal, and a sigma-delta modulator comprising an input for receiving a multi-bit input signal indicative of at least part of the divisor value. The input of the sigma-delta modulator is coupled with the dithering circuit for receiving the dither signal as a most significant bit of the multi-bit input signal.

摘要翻译： 一种频率合成器电路，其减少不期望的寄生边带，同时保持具有锁相环电路的相位噪声性能，该锁相环电路至少包括相位检测器，受控振荡器，耦合到受控振荡器的分频器，用于响应于调整分频器的分频 涉及从除数值产生的接收控制信号，用于提供抖动信号的抖动电路，以及包括用于接收指示除数值的至少一部分的多位输入信号的输入的Σ-Δ调制器。 Σ-Δ调制器的输入与抖动电路耦合，用于接收抖动信号作为多位输入信号的最高有效位。

公开(公告)号：US08921475B2

公开(公告)日：2014-12-30

申请号：US13384611

申请日：2010-07-19

申请人： Joachim W. Zech ,  Thomas Klettke ,  Sebastian Zeller ,  Bernd Kuppermann ,  Hendrik Grupp

发明人： Joachim W. Zech ,  Thomas Klettke ,  Sebastian Zeller ,  Bernd Kuppermann ,  Hendrik Grupp

IPC分类号： C08K3/34 ,  B22F1/00 ,  C08C1/06 ,  C08K3/00 ,  C08F2/44 ,  C08G61/02 ,  G21F9/00 ,  C08F2/46 ,  A61K6/10

CPC分类号： A61K6/10 ,  A61C9/0026 ,  A61K6/087

摘要： The invention relates to a hardenable dental composition comprising component (A) comprising a cationically hardenable compound, component (B) comprising an initiator being able to initiate the hardening reaction of the cationically hardenable compound, and component (C) comprising a filler, wherein the filler comprises a filler body and a filler surface, the filler surface comprising side groups with polar moieties. The invention also relates to a process of producing the dental composition, to the use of the dental composition as dental impression material and to a method of taking an impression of dental tissue.

摘要翻译： 本发明涉及一种可硬化牙科用组合物，其包含包含阳离子可硬化化合物的组分（A），组分（B），其包含能够引发阳离子可硬化化合物的硬化反应的引发剂和包含填料的组分（C），其中 填料包括填料体和填料表面，填料表面包含具有极性部分的侧基。 本发明还涉及一种生产牙科用组合物的方法，该牙科用组合物用作牙科印模材料，以及一种采取牙科印模的方法。

公开(公告)号：US20110109390A1

公开(公告)日：2011-05-12

申请号：US13006246

申请日：2011-01-13

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： H03F3/45

CPC分类号： H03F3/45085 ,  H03F1/0261 ,  H03F3/195 ,  H03F3/4508 ,  H03F2200/294 ,  H03F2200/36 ,  H03F2200/375 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45362 ,  H03F2203/45382 ,  H03F2203/45384 ,  H03F2203/45392 ,  H03F2203/45486 ,  H03F2203/45496

摘要： A transconductor circuit, particularly according to the multi-tanh principle, having a first input node and a second input node, a first differential amplifier coupled to the first and second input nodes, and having a first offset voltage, and a second differential amplifier coupled to the first and second input nodes, and having a second offset voltage different from the first offset voltage. A first resistance circuit is coupled between the first differential amplifier and at least one current source, and a second resistance circuit is coupled between the second differential amplifier and the at least one current source. Varying of the current sources enables control of the transconductance without degrading linearity.

摘要翻译： 具有第一输入节点和第二输入节点的多导体电路特别是多导体电路，耦合到第一和第二输入节点并且具有第一偏移电压的第一差分放大器和耦合到第一输入节点的第二差分放大器 到第一和第二输入节点，并且具有不同于第一偏移电压的第二偏移电压。 第一电阻电路耦合在第一差分放大器和至少一个电流源之间，第二电阻电路耦合在第二差分放大器与至少一个电流源之间。 电流源的变化使得可以控制跨导而不降低线性度。

公开(公告)号：US20110102032A1

公开(公告)日：2011-05-05

申请号：US12608788

申请日：2009-10-29

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： H03L7/085

CPC分类号： H03L7/093

摘要： A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node. such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

摘要翻译： 一种环路滤波器，具有在其上接收到环路滤波器的输入信号的第一节点，在其上提供环路滤波器的输出信号的第二节点以及至少产生零的第一电路的级联布置， 产生第一极的第二电路和产生第二极以形成至少三阶的无源环路滤波器的第三电路。 级联布置包括将第一节点耦合到第二节点的第一信号路径。 使得第一电路通过第二电路和第三电路耦合到第一节点。 此外，环路滤波器包括至少一个晶体管电路和在第一节点并联耦合到第一信号路径的第二信号路径，并通过晶体管电路耦合到第二节点。

公开(公告)号：US08749416B2

公开(公告)日：2014-06-10

申请号：US13280004

申请日：2011-10-24

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： H03M3/00

CPC分类号： H03M3/344 ,  H03M3/43 ,  H03M3/456

摘要： A continuous time sigma-delta analog-to-digital converter comprising: a summator of an input analog signal and a feedback signal; a feed-forward integrator path connected to the summator and configured to provide a digital signal; a feedback digital-to-analog converter to convert the digital signal into a feedback analog signal; a feedback low pass filter structured to filter the feedback analog signal and provide the feedback signal to the summator.

摘要翻译： 一种连续时间Σ-Δ模数转换器，包括：输入模拟信号和反馈信号的加法器; 前馈积分器路径，其连接到所述求和器并且被配置为提供数字信号; 反馈数模转换器，用于将数字信号转换为反馈模拟信号; 反馈低通滤波器，被构造为对反馈模拟信号进行滤波并将反馈信号提供给求和器。

公开(公告)号：US20120187017A1

公开(公告)日：2012-07-26

申请号：US13384611

申请日：2010-07-19

申请人： Joachim W. Zech ,  Thomas Klettke ,  Sebastian Zeller ,  Bernd Kuppermann ,  Hendrik Grupp

发明人： Joachim W. Zech ,  Thomas Klettke ,  Sebastian Zeller ,  Bernd Kuppermann ,  Hendrik Grupp

IPC分类号： B65D85/00 ,  A61K6/10

CPC分类号： A61K6/10 ,  A61C9/0026 ,  A61K6/087

摘要： The invention relates to a hardenable dental composition comprising component (A) comprising a cationically hardenable compound, component (B) comprising an initiator being able to initiate the hardening reaction of the cationically hardenable compound, and component (C) comprising a filler, wherein the filler comprises a filler body and a filler surface, the filler surface comprising side groups with polar moieties. The invention also relates to a process of producing the dental composition, to the use of the dental composition as dental impression material and to a method of taking an impression of dental tissue.

摘要翻译： 本发明涉及一种可硬化牙科用组合物，其包含包含阳离子可硬化化合物的组分（A），组分（B），其包含能够引发阳离子可硬化化合物的硬化反应的引发剂和包含填料的组分（C），其中 填料包括填料体和填料表面，填料表面包含具有极性部分的侧基。 本发明还涉及一种生产牙科用组合物的方法，该牙科用组合物用作牙科印模材料，以及一种采取牙科印模的方法。

公开(公告)号：US20110103541A1

公开(公告)日：2011-05-05

申请号：US12610105

申请日：2009-10-30

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： G11C19/00 ,  H03B19/06

CPC分类号： G11C19/00 ,  H03K23/665

摘要： A frequency divider having a plurality of programmable latches connected in a feedback shift register configuration. A programmable latch of said plurality of latches comprises a program input to receive a program signal configured to select a polarity of the programmable latch among two opposite polarities. The frequency divider having a configuration module structured to provide at least the program signal to the program input to modify a divisor parameter of the frequency divider.

摘要翻译： 一种分频器，具有以反馈移位寄存器配置连接的多个可编程锁存器。 所述多个锁存器的可编程锁存器包括用于接收被配置为在两个相反极性中选择可编程锁存器的极性的编程信号的程序输入。 所述分频器具有配置模块，该配置模块被构造成至少向编程输入提供编程信号以修改分频器的除数参数。

公开(公告)号：US20110102063A1

公开(公告)日：2011-05-05

申请号：US12610109

申请日：2009-10-30

申请人： Sebastian Zeller

发明人： Sebastian Zeller

IPC分类号： G05F1/00

CPC分类号： H03G1/0052

摘要： A current-controlled resistor comprises a first input terminal configured to receive an input signal and a second input terminal configured to receive a current control signal. The resistor comprises a first stage configured to receive the current control signal; the first stage includes first and second PN diodes having first terminals of a first type and second terminals of a second type. The first terminals of the first and second PN diodes are coupled each other and a second terminal of the first PN diode is coupled to the first input terminal. The resistor comprises a second stage configured to receive the current control signal; the second stage includes a third PN diode having first and second terminals of the first and second types, the second terminal of the third PN diode being coupled to the second terminal of the second PN diode.

摘要翻译： 电流控制电阻器包括被配置为接收输入信号的第一输入端子和被配置为接收电流控制信号的第二输入端子。 电阻器包括被配置为接收电流控制信号的第一级; 第一级包括具有第一类型的第一端子和第二类型的第二端子的第一和第二PN二极管。 第一和第二PN二极管的第一端子彼此耦合，并且第一PN二极管的第二端子耦合到第一输入端子。 电阻器包括被配置为接收电流控制信号的第二级; 第二级包括具有第一和第二类型的第一和第二端子的第三PN二极管，第三PN二极管的第二端子耦合到第二PN二极管的第二端子。

公开(公告)号：US08185080B2

公开(公告)日：2012-05-22

申请号：US12609517

申请日：2009-10-30

申请人： Sebastian Zeller ,  Peter Kirchlechner ,  Martin Frey

发明人： Sebastian Zeller ,  Peter Kirchlechner ,  Martin Frey

IPC分类号： H04B1/26

CPC分类号： H03D7/18 ,  H03D2200/0086

摘要： A harmonic rejection mixer for carrying out a frequency translation of a mixer input signal having a mixer input frequency, the mixer including an up-conversion mixer for generating an intermediate signal by multiplying the mixer input signal with a first local oscillation signal having a first local oscillation frequency, and a down-conversion mixer for generating a mixer output signal by multiplying the intermediate signal with a second local oscillation signal having a second local oscillation frequency. The first local oscillation frequency and the second local oscillation frequency are greater than the mixer input frequency. The first local oscillation signal is an l-time oversampled sine wave and the second local oscillation signal is an m-time oversampled sine wave.

摘要翻译： 一种谐波抑制混频器，用于对具有混频器输入频率的混频器输入信号进行频率转换，所述混频器包括用于通过将混频器输入信号与具有第一本地信号的第一本地振荡信号相乘产生中间信号的上变频混频器 振荡频率和下变频混频器，用于通过将中间信号与具有第二本地振荡频率的第二本地振荡信号相乘来产生混频器输出信号。 第一本地振荡频率和第二本地振荡频率大于混频器输入频率。 第一本地振荡信号是1次过采样正弦波，第二本地振荡信号是m次过采样正弦波。