公开(公告)号：US08924761B2

公开(公告)日：2014-12-30

申请号：US13088155

申请日：2011-04-15

申请人： Sei Baba ,  Takeshi Shimanuki ,  Eiji Kimura

发明人： Sei Baba ,  Takeshi Shimanuki ,  Eiji Kimura

IPC分类号： G06F1/00 ,  G06F1/24

CPC分类号： G06F1/24 ,  G06F1/266

摘要： A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

摘要翻译： 采用复位控制器，其执行用于使外部复位端子被共享用于复位信号的外部输出和从外部输入复位信号的控制，允许来自外部复位端子的复位输入处于电源 电压稳定，并且当由检测电路检测到由于电源电压接通或电源电压电平降低引起的复位因素时，输出/输出缓冲器将复位信号输出到 外部复位端子，并使用由检测电路检测的信号来掩蔽复位信号从输入/输出缓冲器到其输入路径的流入。 假设屏蔽周期是比从复位指令到复位释放的周期更长的时间段。

公开(公告)号：US20110258428A1

公开(公告)日：2011-10-20

申请号：US13088155

申请日：2011-04-15

申请人： Sei BABA ,  Takeshi Shimanuki ,  Eiji Kimura

发明人： Sei BABA ,  Takeshi Shimanuki ,  Eiji Kimura

IPC分类号： G06F1/24

CPC分类号： G06F1/24 ,  G06F1/266

摘要： A reset controller is adopted which performs control for causing an external reset terminal to be shared for external output of a reset signal and input of a reset signal from outside, allowing a reset input from the external reset terminal in a state in which a power supply voltage is stable, and causing, when a reset factor due to turn-on of a power supply voltage or a reduction in the level of the power supply voltage is detected by a detection circuit, an input/output buffer to output a reset signal to the external reset terminal and masking the inflow of the reset signal from the input/output buffer to its input path, using a signal detected by the detection circuit. A mask period is assumed to be a period longer than a period from reset instructions to a reset release.

摘要翻译： 采用复位控制器，其执行用于使外部复位端子被共享用于复位信号的外部输出并从外部输入复位信号的控制，允许来自外部复位端子的复位输入处于电源 电压稳定，并且当由检测电路检测到由于电源电压接通或电源电压电平降低引起的复位因素时，输出/输出缓冲器将复位信号输出到 外部复位端子，并使用由检测电路检测的信号来掩蔽复位信号从输入/输出缓冲器到其输入路径的流入。 假设屏蔽周期是比从复位指令到复位释放的周期更长的时间段。

公开(公告)号：US07109779B2

公开(公告)日：2006-09-19

申请号：US11153355

申请日：2005-06-16

申请人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

发明人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

IPC分类号： H03L5/00

CPC分类号： H03K19/018585 ,  H03K19/01855

摘要： A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

摘要翻译： 半导体集成电路包括具有高于第一电路的击穿电压的第一电路和第二电路。 可以使第一和第二电路的工作电压彼此相等或不同。 第二电路具有电平移位电路，用于根据第二电路的操作电压来移位第一电路的输出信号的电平，外部输出缓冲器具有可以选择性地接收电平的输出信号的输入 移位电路或旁路电平移位电路的输入信号。 当第一和第二电路以低电压工作时，选择旁路。 在高压运行和老化期间，选择电平移位电路。

公开(公告)号：US20050231262A1

公开(公告)日：2005-10-20

申请号：US11153355

申请日：2005-06-16

申请人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

发明人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

IPC分类号： G01R31/30 ,  G01R31/28 ,  G01R31/316 ,  H01L21/822 ,  H01L27/04 ,  H03K19/0175 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018585 ,  H03K19/01855

摘要： A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.

摘要翻译： 半导体集成电路包括具有高于第一电路的击穿电压的第一电路和第二电路。 可以使第一和第二电路的工作电压彼此相等或不同。 第二电路具有电平移位电路，用于根据第二电路的操作电压来移位第一电路的输出信号的电平，外部输出缓冲器具有可以选择性地接收电平的输出信号的输入 移位电路或旁路电平移位电路的输入信号。 当第一和第二电路以低电压工作时，选择旁路。 在高压运行和老化期间，选择电平移位电路。

公开(公告)号：US5259000A

公开(公告)日：1993-11-02

申请号：US236917

申请日：1988-09-23

申请人： Yasuyuki Kojima ,  Yasushi Yokosuka ,  Takeshi Shimanuki ,  Kazuhiko Takaoka ,  Yukihito Ishihara

发明人： Yasuyuki Kojima ,  Yasushi Yokosuka ,  Takeshi Shimanuki ,  Kazuhiko Takaoka ,  Yukihito Ishihara

IPC分类号： H04L27/00 ,  H04M11/06 ,  H04B1/38

CPC分类号： H04L27/0008 ,  H04M11/06

摘要： In a MODEM having modulation and demodulation circuits and a circuit for controlling the modulation and demodulation, a modulator-demodulator apparatus includes a register for accepting a macro-instruction from an external source; a circuit for interpreting and executing the macro-instruction; and a circuit for outputting a response to the macro-instruction, whereby the MODEM is controlled in response to the macro-instruction accepted from the outside source. The modulator-demodulator apparatus is suitably integrated over a single semiconductor substrate.

摘要翻译： 在具有调制和解调电路的调制解调器和用于控制调制和解调的电路的调制解调器中，调制器 - 解调器装置包括用于从外部源接受宏指令的寄存器; 用于解释和执行宏指令的电路; 以及用于输出对宏指令的响应的电路，由此响应于从外部源接受的宏指令来控制MODEM。 调制解调器装置适当地集成在单个半导体衬底上。

公开(公告)号：US07238850B2

公开(公告)日：2007-07-03

申请号：US11360461

申请日：2006-02-23

申请人： Takeshi Shimanuki

发明人： Takeshi Shimanuki

IPC分类号： A61F13/00 ,  A61F15/00

CPC分类号： B32B7/02 ,  A61F13/0203 ,  A61F2013/00463 ,  A61F2013/0091 ,  A61F2013/00914 ,  A61L15/42 ,  A61L2400/04 ,  B32B3/266 ,  B32B9/02 ,  B32B9/04 ,  B32B2305/026 ,  B32B2307/726 ,  B32B2307/7265

摘要： A hemostasis tool is provided for stopping bleeding by absorbing blood from the wound and having blood diffusion and absorption abilities, which includes a lamination comprising a water-permeable inner material on a wound side, a water-impermeable outer material on a side departing from the wound side, a pulp-cotton laminated body between the inner and outer materials, a crust between the pulp-cotton laminated body and the water-impermeable outer material for diffusing the blood that has passed through the water-permeable inner material and the pulp-cotton laminated body, and a polymer for absorbing the blood diffused by the crust. Instead of the pulp-cotton laminated body, a synthesis fiber laminated body can be utilized in the hemostasis tool having a laminated structure. The hemostasis tool serves to actively diffuse transmitted blood by a crust disposed in the intermediate layer of a hemostasis tool, and to improve the absorbing ability of the blood with a polymer that is polymeric absorbing material disposed at an outer part than the crust.

摘要翻译： 提供一种止血工具，用于通过从伤口吸收血液并具有血液扩散和吸收能力来阻止出血，其包括在缠绕侧上包括透水内部材料的层压体，在离开所述侧壁的侧面上的不透水的外部材料 内侧和外部材料之间的纸浆棉层压体，纸浆棉层压体与不透水外部材料之间的外壳，用于使已经通过透水性内部材料和纸浆 - 棉层压体和用于吸收由地壳扩散的血液的聚合物。 代替纸浆棉层压体，可以在具有层压结构的止血工具中使用合成纤维层压体。 止血工具用于通过设置在止血工具的中间层中的外壳积极地扩散透射的血液，并且利用聚合物吸收材料提高血液的吸收能力，所述聚合物是位于外壳外部的聚合物吸收材料。

公开(公告)号：US07170114B2

公开(公告)日：2007-01-30

申请号：US10956140

申请日：2004-10-04

申请人： Takeshi Shimanuki

发明人： Takeshi Shimanuki

IPC分类号： H01L27/10 ,  H01L23/48

CPC分类号： G11C7/1057 ,  G11C5/025 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/49171 ,  H01L2924/00

摘要： A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n−2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.

摘要翻译： 通过提供I / O缓冲器的有效布局，芯片尺寸显着降低。 由于设置了大容量的非易失性存储器，所以在矩形半导体芯片的每一侧附近的区域配置接合焊盘，并且在这些接合焊盘的内部电路区域的侧面配置有I / O缓冲器。 在该半导体芯片中，长边侧的I / O缓冲器的数量大于半导体芯片的短边侧的I / O缓冲器的数量。 例如，n个I / O缓冲器分别布置在两个较长边的一侧，而（n-2）个I / O缓冲器分别布置在两个短边的一侧。 因此，可以布置I / O缓冲器而不用增加芯片面积。

公开(公告)号：US06777997B2

公开(公告)日：2004-08-17

申请号：US10309183

申请日：2002-12-04

申请人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

发明人： Shigemitsu Tahara ,  Daisuke Katagiri ,  Takeshi Shimanuki ,  Masashi Oshiba

IPC分类号： H03L500

CPC分类号： H03K19/018585 ,  H03K19/01855

摘要： The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other. The second circuit has a plurality of level shift circuits capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit, a plurality of external output buffers receiving outputs of the level shift circuits, bypasses for bypassing an input of a predetermined level shift circuit to an input of a predetermined external output buffer, and a selecting circuit for selecting connection of either the predetermined level shift circuit or a bypass to an input of the predetermined external output buffer. In a use form in which the first and second circuits operate with a low voltage, the bypass is selected. In high-voltage operation and burn-in, the level shift circuits are selected.

摘要翻译： 从防止由于电平移位电路的输出操作延迟和维持输出缓冲器的高击穿电压的观点来看，本发明实现了与时钟信号同步的更高速的外部输出操作。 半导体集成电路包括具有比第一电路的击穿电压高的击穿电压的第一电路和第二电路，并且可以使第一和第二电路的操作电压彼此相等或不同。 第二电路具有多个电平移位电路，能够根据第二电路的工作电压来移动第一电路的输出电平，接收电平移位电路的输出的多个外部输出缓冲器，用于旁路的旁路 将预定电平移位电路输入到预定的外部输出缓冲器的输入端，以及选择电路，用于选择预定电平移位电路或旁路中的任一者与预定外部输出缓冲器的输入端的连接。 在第一和第二电路以低电压工作的使用形式中，选择旁路。 在高压运行和老化期间，选择电平移位电路。

公开(公告)号：US20070100271A1

公开(公告)日：2007-05-03

申请号：US11360461

申请日：2006-02-23

申请人： Takeshi Shimanuki

发明人： Takeshi Shimanuki

IPC分类号： A61F13/00

CPC分类号： B32B7/02 ,  A61F13/0203 ,  A61F2013/00463 ,  A61F2013/0091 ,  A61F2013/00914 ,  A61L15/42 ,  A61L2400/04 ,  B32B3/266 ,  B32B9/02 ,  B32B9/04 ,  B32B2305/026 ,  B32B2307/726 ,  B32B2307/7265

摘要： A hemostasis tool is provided for stopping bleeding by absorbing blood from the wound and having blood diffusion and absorption abilities, which includes a lamination comprising a water-permeable inner material on a wound side, a water-impermeable outer material on a side departing from the wound side, a pulp-cotton laminated body between the inner and outer materials, a crust between the pulp-cotton laminated body and the water-impermeable outer material for diffusing the blood that has passed through the water-permeable inner material and the pulp-cotton laminated body, and a polymer for absorbing the blood diffused by the crust. Instead of the pulp-cotton laminated body, a synthesis fiber laminated body can be utilized in the hemostasis tool having a laminated structure. The hemostasis tool serves to actively diffuse transmitted blood by a crust disposed in the intermediate layer of a hemostasis tool, and to improve the absorbing ability of the blood with a polymer that is polymeric absorbing material disposed at an outer part than the crust.

摘要翻译： 提供一种止血工具，用于通过从伤口吸收血液并具有血液扩散和吸收能力来阻止出血，其包括在缠绕侧上包括透水内部材料的层压体，在离开所述侧壁的侧面上的不透水的外部材料 内侧和外部材料之间的纸浆棉层压体，纸浆棉层压体与不透水外部材料之间的外壳，用于使已经通过透水性内部材料和纸浆 - 棉层压体和用于吸收由地壳扩散的血液的聚合物。 代替纸浆棉层压体，可以在具有层压结构的止血工具中使用合成纤维层压体。 止血工具用于通过设置在止血工具的中间层中的外壳积极地扩散透射的血液，并且利用聚合物吸收材料提高血液的吸收能力，所述聚合物是位于外壳外部的聚合物吸收材料。

公开(公告)号：US20050078540A1

公开(公告)日：2005-04-14

申请号：US10956140

申请日：2004-10-04

申请人： Takeshi Shimanuki

发明人： Takeshi Shimanuki

IPC分类号： H01L27/04 ,  G11C5/02 ,  G11C7/10 ,  H01L21/82 ,  H01L21/822 ,  G11C11/34

CPC分类号： G11C7/1057 ,  G11C5/025 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/49171 ,  H01L2924/00

摘要： A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n−2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.

摘要翻译： 通过提供I / O缓冲器的有效布局，芯片尺寸显着降低。 由于设置了大容量的非易失性存储器，所以在矩形半导体芯片的每一侧附近的区域配置接合焊盘，并且在这些接合焊盘的内部电路区域的侧面配置有I / O缓冲器。 在该半导体芯片中，长边侧的I / O缓冲器的数量大于半导体芯片的短边侧的I / O缓冲器的数量。 例如，n个I / O缓冲器分别布置在两个较长边的一侧，而（n-2）个I / O缓冲器分别布置在两个短边的一侧。 因此，可以布置I / O缓冲器而不用增加芯片面积。