公开(公告)号：US20130033936A1

公开(公告)日：2013-02-07

申请号：US13204014

申请日：2011-08-05

申请人： Seiichi ARITOME ,  Soojin Wi ,  Angelo Visconti ,  Silvia Beltrami ,  Christian Monzio Compagnoni ,  Alessandro Sottocornola Spinelli

发明人： Seiichi ARITOME ,  Soojin Wi ,  Angelo Visconti ,  Silvia Beltrami ,  Christian Monzio Compagnoni ,  Alessandro Sottocornola Spinelli

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3404 ,  G11C11/5628 ,  G11C16/3459

摘要： Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.

摘要翻译： 公开了用于操作存储器单元的存储器件和方法，诸如使用两个程序验证电平（例如，低程序验证电平和程序验证电平）来确定如何增加数据线电压的方法。 确定已经用编程电压偏置的存储单元的阈值电压，并确定其与两个程序验证电平的关系。 如果阈值电压小于低编程验证电平，则可以将数据线偏置在接地电压（例如0V）以用于随后的编程脉冲。 如果阈值电压大于程序验证电平，则数据线可以被偏置在用于后续编程脉冲的禁止电压。 如果阈值电压在两个程序验证电平之间，则对于其中阈值电压在两个程序验证电平之间的每个后续编程脉冲，可以增加数据线电压。

公开(公告)号：US20120275227A1

公开(公告)日：2012-11-01

申请号：US13549743

申请日：2012-07-16

申请人： Seiichi ARITOME ,  Haitao Liu ,  Di Li

发明人： Seiichi ARITOME ,  Haitao Liu ,  Di Li

IPC分类号： G11C16/04

CPC分类号： G11C16/12

摘要： A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.

摘要翻译： 用于防止短沟道源侧选择栅极结构中的穿通的编程方法和存储器结构包括调整所选择和未选择的位线上的电压以及编程，通过和选择栅极电压。

公开(公告)号：US20120163093A1

公开(公告)日：2012-06-28

申请号：US13331820

申请日：2011-12-20

申请人： Seiichi ARITOME ,  Soon Ok Seo

发明人： Seiichi ARITOME ,  Soon Ok Seo

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A programming method of a nonvolatile memory device includes inputting even data and odd data to be programmed into even memory cells coupled to even bit lines and odd memory cells coupled to odd bit lines, respectively, setting a sense signal as a first sense signal or a second sense signal having a lower voltage level than the first sense signal, based on odd data of odd memory cells adjacent to each of the even memory cells to be programmed, programming the even data into the even memory cells by supplying a program voltage, performing a program verify operation on each of the even memory cells in response to the set sense signal, and programming the odd data into the odd memory cells by supplying a program voltage.

摘要翻译： 非易失性存储器件的编程方法包括：将要编程的偶数数据和奇数数据分别输入耦合到偶位线的偶数存储器单元和耦合到奇数位线的奇数存储单元，将感测信号设置为第一感测信号或 基于与要编程的每个偶数存储器单元相邻的奇数存储器单元的奇数数据，具有比第一感测信号低的电压电平的第二感测信号，通过提供编程电压将偶数数据编程到偶数存储单元中，执行 响应于所设置的感测信号对每个偶数存储单元进行程序验证操作，并通过提供编程电压将奇数数据编程到奇数存储单元中。

公开(公告)号：US20110032772A1

公开(公告)日：2011-02-10

申请号：US12832105

申请日：2010-07-08

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L29/66825 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L29/78642 ,  H01L29/7881

摘要： A vertical channel type non-volatile memory device having a plurality of memory cells stacked along a channel includes the channel configured to be protruded from a substrate, a tunnel insulation layer configured to surround the channel, a plurality of floating gate electrodes and a plurality of control gate electrodes configured to be alternately stacked along the channel, and a charge blocking layer interposed between the plurality of the floating gate electrodes and the plurality of the control gate electrodes alternately stacked.

摘要翻译： 具有沿着沟道堆叠的多个存储单元的垂直沟道型非易失性存储器件包括被配置为从衬底突出的沟道，被配置为围绕沟道的隧道绝缘层，多个浮栅电极和多个 配置为沿通道交替层叠的控制栅极电极和交替堆叠在多个浮置栅电极和多个控制栅极电极之间插入的电荷阻挡层。

公开(公告)号：US20130010547A1

公开(公告)日：2013-01-10

申请号：US13542372

申请日：2012-07-05

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/06

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3427

摘要： A method of operating a semiconductor device includes programming selected memory cells by supplying a selected word line with a program voltage which increases and supplying the remaining unselected word lines with a first pass voltage which is substantially constant; and programming the selected memory cells while supplying first unselected word lines adjacent to the selected word line with a second pass voltage increasing in proportion to the program voltage, when a difference between the program voltage and the first pass voltage reaches a critical voltage difference.

摘要翻译： 一种操作半导体器件的方法包括通过向所选择的字线提供编程电压来对选定的存储器单元进行编程，所述编程电压增加并提供剩余的未选择字线，所述第一通过电压基本上是恒定的; 以及当所述编程电压和所述第一通过电压之间的差达到临界电压差时，以与所述编程电压成比例的方式增加的第二通过电压来提供与所述选定字线相邻的第一未选字线。

公开(公告)号：US20120307565A1

公开(公告)日：2012-12-06

申请号：US13353429

申请日：2012-01-19

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/3409

摘要： A method for operating a non-volatile memory device includes performing an erase operation onto a memory block including a plurality of memory cells, and performing a first soft program operation onto all the memory cells of a string, after the erase operation, grouping word lines of the string into a plurality of word line groups, and performing a second soft program operation onto memory cells coupled with the word lines of each word line group.

摘要翻译： 一种用于操作非易失性存储器件的方法包括在包括多个存储器单元的存储器块上执行擦除操作，并且在擦除操作之后对字符串的所有存储单元执行第一软编程操作，将字线 并且对与每个字线组的字线耦合的存储器单元执行第二软编程操作。

公开(公告)号：US20120176838A1

公开(公告)日：2012-07-12

申请号：US13428241

申请日：2012-03-23

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A method for programming that biases a selected word line with a programming voltage. An unselected word line on the source side and an unselected word line on the drain side of the selected word line are biased at a pass voltage that is less than the normal pass voltage. These unselected word lines are both located a predetermined distance from the selected word line. The remaining word lines are biased at the normal pass voltage.

摘要翻译： 一种用编程电压偏置选定字线的编程方法。 源极侧的未选字线和所选择的字线的漏极侧的未选字线被偏置在小于正常通过电压的通过电压。 这些未选择的字线都位于与所选字线预定的距离处。 剩下的字线以正常通过电压偏置。

公开(公告)号：US20130010549A1

公开(公告)日：2013-01-10

申请号：US13542487

申请日：2012-07-05

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/00

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/3427

摘要： A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference.

摘要翻译： 根据本发明的实施例的操作半导体器件的方法包括通过对选定的字线施加逐渐上升的第一编程电压并将恒定的第一通过电压施加到剩余的未选择来对所选存储单元进行编程 字线 以及对所选择的字线施加恒定的第二编程电压，并且对所选择的字线相邻的第一未选字线施加逐渐上升的第二通过电压，对所选存储单元进行编程， 第一编程电压和第一通过电压达到临界电压差。

公开(公告)号：US20130010548A1

公开(公告)日：2013-01-10

申请号：US13542401

申请日：2012-07-05

申请人： Seiichi ARITOME

发明人： Seiichi ARITOME

IPC分类号： G11C7/00

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3427

摘要： A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.

摘要翻译： 半导体器件尤其通过以下方式操作：通过将第一编程电压施加第一步骤电压至所选择的字线并通过向未选择的字线施加具有恒定电平的第一通过电压来对选定的存储器单元进行编程;以及 当第一编程电压和第一通过电压之间的电压差达到预定的电压差时，通过将第二编程电压施加到比所述第一阶跃电压低的第二阶跃电压的第二编程电压来对所选择的存储单元进行编程， 并且通过将与第二编程电压成比例地增加的第二通过电压施加到未选择字线中与所选字线相邻的第一未选择字线。

公开(公告)号：US20120170371A1

公开(公告)日：2012-07-05

申请号：US13334423

申请日：2011-12-22

申请人： Seiichi ARITOME ,  Hyun-Seung Yoo ,  Sung-Jin Whang

发明人： Seiichi ARITOME ,  Hyun-Seung Yoo ,  Sung-Jin Whang

IPC分类号： G11C16/10

CPC分类号： G11C16/3427 ,  G11C16/0483 ,  H01L27/11556

摘要： A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.

摘要翻译： 一种非易失性存储器件的编程方法，包括具有多个浮动栅极和多个控制栅极交替布置的存储器单元串，其中每个存储器单元包括一个浮置栅极和两个控制栅极， 浮动门和两个相邻的存储单元共享一个控制门。 编程方法包括将第一编程电压施加到所选择的存储单元的第一控制栅极，以及将高于第一编程电压的第二编程电压施加到所选存储单元的第二控制栅极，并将第一通过电压施加到 与第一控制栅极相邻设置的第三控制栅极和与第二控制栅极相邻设置的第四控制栅极低于第一通过电压的第二通过电压。