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    Methods to operate a memory cell
    3.
    发明授权
    Methods to operate a memory cell 有权
    操作存储单元的方法

    公开(公告)号：US08619475B2

    公开(公告)日：2013-12-31

    申请号：US13204014

    申请日：2011-08-05

    申请人： Seiichi Aritome ,  Soojin Wi ,  Angelo Visconti ,  Silvia Beltrami ,  Christian Monzio Compagnoni ,  Alessandro Sottocornola Spinelli

    发明人： Seiichi Aritome ,  Soojin Wi ,  Angelo Visconti ,  Silvia Beltrami ,  Christian Monzio Compagnoni ,  Alessandro Sottocornola Spinelli

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3404 ,  G11C11/5628 ,  G11C16/3459

    摘要： Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.

    摘要翻译： 公开了用于操作存储器单元的存储器件和方法，诸如使用两个程序验证电平（例如，低程序验证电平和程序验证电平）来确定如何增加数据线电压的方法。 确定已经用编程电压偏置的存储单元的阈值电压，并确定其与两个程序验证电平的关系。 如果阈值电压小于低编程验证电平，则可以将数据线偏置在接地电压（例如0V）以用于随后的编程脉冲。 如果阈值电压大于程序验证电平，则数据线可以被偏置在用于后续编程脉冲的禁止电压。 如果阈值电压在两个程序验证电平之间，则对于其中阈值电压在两个程序验证电平之间的每个后续编程脉冲，可以增加数据线电压。

    METHODS TO OPERATE A MEMORY CELL
    4.
    发明申请
    METHODS TO OPERATE A MEMORY CELL 有权
    操作记忆体的方法

    公开(公告)号：US20130033936A1

    公开(公告)日：2013-02-07

    申请号：US13204014

    申请日：2011-08-05

    申请人： Seiichi ARITOME ,  Soojin Wi ,  Angelo Visconti ,  Silvia Beltrami ,  Christian Monzio Compagnoni ,  Alessandro Sottocornola Spinelli

    发明人： Seiichi ARITOME ,  Soojin Wi ,  Angelo Visconti ,  Silvia Beltrami ,  Christian Monzio Compagnoni ,  Alessandro Sottocornola Spinelli

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C16/3404 ,  G11C11/5628 ,  G11C16/3459

    摘要： Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.

    摘要翻译： 公开了用于操作存储器单元的存储器件和方法，诸如使用两个程序验证电平（例如，低程序验证电平和程序验证电平）来确定如何增加数据线电压的方法。 确定已经用编程电压偏置的存储单元的阈值电压，并确定其与两个程序验证电平的关系。 如果阈值电压小于低编程验证电平，则可以将数据线偏置在接地电压（例如0V）以用于随后的编程脉冲。 如果阈值电压大于程序验证电平，则数据线可以被偏置在用于后续编程脉冲的禁止电压。 如果阈值电压在两个程序验证电平之间，则对于其中阈值电压在两个程序验证电平之间的每个后续编程脉冲，可以增加数据线电压。

    Nand flash memory with reduced programming disturbance
    6.
    发明申请
    Nand flash memory with reduced programming disturbance 有权
    Nand闪存，减少编程干扰

    公开(公告)号：US20080068890A1

    公开(公告)日：2008-03-20

    申请号：US11901596

    申请日：2007-09-17

    申请人： Silvia Beltrami ,  Angelo Visconti

    发明人： Silvia Beltrami ,  Angelo Visconti

    IPC分类号： G11C16/02

    CPC分类号： G11C7/02 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/12

    摘要： An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

    摘要翻译： 具有NAND架构的闪速存储器件的实施例，包括每个具有可编程阈值电压的数据存储单元矩阵，其中所述矩阵被布置成多个行和列，每行的存储单元连接到 对应的字线和每列的存储单元被布置在多个存储单元串中，每个串中的存储单元串联连接，每列的串耦合到参考电压分配线，该参考电压分配线通过 第一选择器的装置，其中每个串还包括插入在所述串的所述存储单元和所述第一选择器之间的至少一个第一屏蔽元件，所述第一屏蔽元件适于屏蔽所述存储器单元与操作中出现的电场 在存储单元串和第一选择器之间。

    NAND flash memory with reduced programming disturbance
    8.
    发明授权
    NAND flash memory with reduced programming disturbance 有权
    NAND闪存具有减少的编程干扰

    公开(公告)号：US07710778B2

    公开(公告)日：2010-05-04

    申请号：US11901596

    申请日：2007-09-17

    申请人： Silvia Beltrami ,  Angelo Visconti

    发明人： Silvia Beltrami ,  Angelo Visconti

    IPC分类号： G11C11/34

    CPC分类号： G11C7/02 ,  G11C5/063 ,  G11C16/0483 ,  G11C16/12

    摘要： An embodiment of a flash memory device with NAND architecture, including a matrix of data storage memory cells each one having a programmable threshold voltage, wherein the matrix is arranged in a plurality of rows and columns with the memory cells of each row being connected to a corresponding word line and the memory cells of each column being arranged in a plurality of strings of memory cells, the memory cells in each string being connected in series, the strings of each column being coupled to a reference voltage distribution line distributing a reference voltage by means of a first selector, wherein each string further includes at least one first shielding element interposed between the memory cells of the string and said first selector, the first shielding element being adapted to shield the memory cells from electric fields that, in operation, arise between the string of memory cells and the first selector.

    摘要翻译： 具有NAND架构的闪速存储器件的实施例，包括每个具有可编程阈值电压的数据存储单元矩阵，其中所述矩阵被布置成多个行和列，每行的存储单元连接到 对应的字线和每列的存储单元被布置在多个存储单元串中，每个串中的存储单元串联连接，每列的串耦合到参考电压分配线，该参考电压分配线通过 第一选择器的装置，其中每个串还包括插入在所述串的所述存储单元和所述第一选择器之间的至少一个第一屏蔽元件，所述第一屏蔽元件适于屏蔽所述存储器单元与操作中出现的电场 在存储单元串和第一选择器之间。