公开(公告)号：US07043202B2

公开(公告)日：2006-05-09

申请号：US10537472

申请日：2003-12-08

申请人： Seiichi Ozawa ,  Junichi Okamura

发明人： Seiichi Ozawa ,  Junichi Okamura

IPC分类号： H04B7/165 ,  H04B1/00

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

公开(公告)号：US20060025094A1

公开(公告)日：2006-02-02

申请号：US10537472

申请日：2003-12-08

申请人： Seiichi Ozawa ,  Junichi Okamura

发明人： Seiichi Ozawa ,  Junichi Okamura

IPC分类号： H04B1/16 ,  H04B1/06 ,  H04B7/00

CPC分类号： G06F1/08 ,  H03K3/0322 ,  H03L7/0996 ,  H03L7/18

摘要： A phase-selective type frequency modulator capable of easing the restriction on a phase range of a modulated clock signal. The phase-selective type frequency modulator includes a multiphase clock signal generating circuit 101 for generating N-phase clock signals; a control circuit 104 for sequentially activating one of first group of clock selection signals indicating a clock signal to be selected from the N-phase clock signals; an edge appearance time adjustment circuit 103 for adjusting a rising edge appearance time and/or a trailing edge appearance time of the first group of clock selection signals outputted from the control circuit 104 to output second group of clock selection signals; and a modulated clock signal generating circuit 102 for selecting one clock signal from the N-phase clock signals in accordance with an activated state of the second group of clock selection signals outputted from the edge appearance time adjustment circuit 103 to output a modulated clock signal MCK.

摘要翻译： 一种相位选择型频率调制器，能够缓和对调制时钟信号的相位范围的限制。 相位选择型频率调制器包括用于产生N相时钟信号的多相时钟信号发生电路101; 控制电路104，用于顺序地激活指示从N相时钟信号中选择的时钟信号的第一组时钟选择信号中的一个; 边缘出现时间调整电路103，用于调整从控制电路104输出的第一组时钟选择信号的上升沿出现时间和/或后沿出现时间，以输出第二组时钟选择信号; 以及调制时钟信号发生电路102，用于根据从边缘出现时间调整电路103输出的第二组时钟选择信号的激活状态从N相时钟信号中选择一个时钟信号，以输出调制时钟信号MCK 。

公开(公告)号：US08363771B2

公开(公告)日：2013-01-29

申请号：US12808598

申请日：2009-10-27

申请人： Hironobu Akita ,  Seiichi Ozawa ,  Yohei Ishizone ,  Satoshi Miura

发明人： Hironobu Akita ,  Seiichi Ozawa ,  Yohei Ishizone ,  Satoshi Miura

IPC分类号： H04L7/04

CPC分类号： H04L7/10 ,  G09G5/008 ,  H03L7/095 ,  H04L7/033 ,  H04L7/046

摘要： Provided are a transmission device, a receiving device, and a communication system having a simple configuration and capable of reliably executing the confirmation of a changed bit rate. The communication system 1 sends, to the receiving device 3, a serial data signal Sdata that is set as a constant value across a period of a constant multiple of a cycle of the clock when a bit rate of a serial data signal Sdata in the transmission device 2 is changed. The receiving device 3 that received the serial data signal Sdata receives training data Tdata from the transmission device 2 when it is determined that the serial data signal Sdata is a constant value across a period of a constant multiple of a cycle of the clock, and proceeds to the processing of confirming the changed bit rate.

摘要翻译： 提供具有简单配置并能够可靠地执行改变的比特率的确认的传输设备，接收设备和通信系统。 通信系统1向发送装置3发送串行数据信号Sdata，该串行数据信号Sdata在传输中的串行数据信号Sdata的比特率时，在时钟周期的恒定倍数的周期内被设置为恒定值 设备2更改。 接收到串行数据信号Sdata的接收装置3当确定串行数据信号Sdata在时钟的周期的恒定倍数的周期内是恒定值时，从发送装置2接收训练数据Tdata，并且进行 以确认改变的比特率的处理。

公开(公告)号：US20120020438A1

公开(公告)日：2012-01-26

申请号：US13263679

申请日：2010-04-12

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H04L27/06

CPC分类号： H04L7/0338

摘要： A reception apparatus is an apparatus for receiving serial data and includes a sampler portion, an edge detection portion, a logical addition operation portion, a timing determination portion, a register portion, a selector portion and a latch portion. The edge detection portion inputs data OSD[n] output from the sampler portion, performs an exclusive OR operation between the data OSD[n] and data OSD[n+1] which are adjacent to each other, and outputs data EDG[n] which is the result of the exclusive OR operation. The logical addition operation portion inputs the data EDG[n] output from the edge detection portion, performs, for a predetermined time period, an OR operation on the data EDG[n], with no used as a reference value, with respect to each n which leaves a remainder of m when a difference (n−no) is divided by a value M, and outputs data EDGFLG[m] which is the result of the OR operation.

摘要翻译： 接收装置是用于接收串行数据的装置，包括采样器部分，边缘检测部分，逻辑加法运算部分，定时确定部分，寄存器部分，选择部分和锁存部分。 边缘检测部分输入从采样器部分输出的数据OSD [n]，执行彼此相邻的数据OSD [n]和数据OSD [n + 1]之间的异或运算，并输出数据EDG [n] 这是异或运算的结果。 逻辑加法运算部输入从边缘检测部输出的数据EDG [n]，对于每一个，对于数据EDG [n]执行与运算不同的参考值的预定时间的“或”运算 当差值（n-no）除以值M时剩下m的余数，并输出作为OR运算结果的数据EDGFLG [m]。

公开(公告)号：US20110285432A1

公开(公告)日：2011-11-24

申请号：US12594916

申请日：2008-10-28

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H03L7/08

CPC分类号： H04L7/033 ,  H04L7/0083 ,  H04L7/0087 ,  H04L25/03012

摘要： A clock data restoration device 1, which restores a clock signal and data on the basis of an inputted digital signal, comprises an equalizer 10, a sampler 20, a clock generator 30, an equalizer controller 40, and a phase monitor 50. A clock signal CK or CKX as a clock signal restored on the basis of the input digital signal is generated through loop processing by the sampler 20 and the clock generator 30. The level adjustment amount of a high frequency component of the digital signal by the equalizer 10 is controlled through loop processing by the equalizer 10, the sampler 20 and the equalizer controller 40.

摘要翻译： 基于输入的数字信号恢复时钟信号和数据的时钟数据恢复装置1包括均衡器10，采样器20，时钟发生器30，均衡器控制器40和相位监视器50.时钟 通过采样器20和时钟发生器30的环路处理产生基于输入数字信号而恢复的时钟信号的信号CK或CKX。均衡器10的数字信号的高频分量的电平调整量为 通过均衡器10，采样器20和均衡器控制器40的环路处理进行控制。

公开(公告)号：US08023606B2

公开(公告)日：2011-09-20

申请号：US12094058

申请日：2006-11-16

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H04L7/0025 ,  H04L7/0087

摘要： With the clock data restoration device 1, as a result of the processing of a loop which comprises the sampler section 10, detection section 20, timing determination section 30, and clock output section 40, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n−2) and value D(n−1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n−2) and value D(n−1) of the preceding two bits are equal to one another.

摘要翻译： 对于时钟数据恢复装置1，作为包括采样器部分10，检测部分20，定时确定部分30和时钟输出部分40的循环处理的结果，时钟信号CKXA的各个相位，时钟信号 CKXB和时钟信号CK被调整以匹配输入数字信号的相位，由时钟信号CKXA指示的数字信号采样时间被调整以匹配数据转换时间分布的峰值时间，在数值D （n-2）和前两个位的值D（n-1）彼此不同，并且调整由时钟信号CKXB指示的数字信号采样时间，以匹配数据转换时间分布的峰值时间 前两位的值D（n-2）和值D（n-1）彼此相等的情况。

公开(公告)号：US20100238951A1

公开(公告)日：2010-09-23

申请号：US12599768

申请日：2008-10-31

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H04L12/66

CPC分类号： H04N21/4408 ,  G06F3/14 ,  G09G3/2092 ,  G09G5/006 ,  G09G5/008 ,  G09G2370/10 ,  H04N21/4122 ,  H04N21/43632 ,  H04N21/4405

摘要： A video transmission device 10 has: a packer 11 which receives a video signal, a sync signal, and a data-enable signal, and generates a plurality of packet signals by packetizing the video signal and the sync signal based on the data-enable signal and according to the number of bytes of a packet corresponding to the number of gradation bits of the video signal; an encode unit 15 which generates a plurality of encoded packet signals by encoding the plurality of packet signals; and a serializer 14 which generates a serial packet signal by parallel-serial converting the plurality of encoded packet signals. The packer 11 generates a control signal including a pulse with a pulse width corresponding to the number of bytes of the packet, and the encode unit 15 subjects a portion of the packet signals corresponding to the pulse in the control signal from the packer, to an encode process which is different from a process for the other portion.

摘要翻译： 视频传输设备10具有：封隔器11，其接收视频信号，同步信号和数据使能信号，并且通过基于数据使能信号分组视频信号和同步信号来产生多个分组信号 并且根据与视频信号的灰度级数相对应的数据包的字节数; 编码单元15，其通过对多个分组信号进行编码来生成多个编码分组信号; 以及串行器14，其通过并行 - 串行转换多个编码分组信号来生成串行分组信号。 封隔器11产生包括具有与分组的字节数相对应的脉冲宽度的脉冲的控制信号，并且编码单元15将来自封隔器的控制信号中与脉冲对应的分组信号的一部分， 编码过程与其他部分的过程不同。

公开(公告)号：US20100026350A1

公开(公告)日：2010-02-04

申请号：US12444607

申请日：2007-09-06

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： H03L7/00

CPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/081 ,  H03L7/091

摘要： A clock/data recovery device 1 comprises a sampler 10, a detector 20, an offset determination part 30, a clock output part 40, and a DA converter 50. The phases of clock signals CK and CKX are adjusted so as to match with the phase of an input digital signal. An offset amount (±Voff) added in the sampler 10 is adjusted so as to match with a peak time of a data transition time distribution of a first signal in a case where a value D(n−1) is HIGH level, and is adjusted so as to match with a peak time of a data transition time distribution of a second signal in a case where the value D(n−1) is LOW level. Either of the clock signals CK and CKX is outputted as the recovered clock signal. Time series data of a digital value D(n) is outputted as the recovered data.

摘要翻译： 时钟/数据恢复装置1包括采样器10，检测器20，偏移确定部分30，时钟输出部分40和DA转换器50.时钟信号CK和CKX的相位被调整为与 输入数字信号的相位。 调整在取样器10中添加的偏移量（±Voff），以便在值D（n-1）为高电平的情况下与第一信号的数据转换时间分布的峰值时间相匹配，并且是 在值D（n-1）为低电平的情况下，调整为与第二信号的数据转换时间分布的峰值时间相匹配。 输出时钟信号CK和CKX中的任一个作为恢复的时钟信号。 输出数字值D（n）的时间序列数据作为恢复数据。

公开(公告)号：US4314957A

公开(公告)日：1982-02-09

申请号：US149161

申请日：1980-05-14

申请人： Seiichi Ozawa

发明人： Seiichi Ozawa

IPC分类号： B28B21/94 ,  C04B41/48 ,  C04B41/63 ,  B28B21/20 ,  B28B21/36

CPC分类号： C04B41/009 ,  B28B21/94 ,  C04B41/48 ,  C04B41/63 ,  Y10S425/014

摘要： A polymer-impregnated concrete product is obtained by placing a concrete mix in a frame capable of withstanding high temperature and high pressure in such a manner as to form therein a hollow portion, molding the concrete mix to obtain a concrete article containing a hollow portion therein, causing the concrete article as held in a tightly closed state in the frame to be cured by application of heat, subjecting the concrete article, as retained in the frame, to treatments for drying and deaeration, then supplying a monomer preparation to the hollow portion of the concrete article, applying pressure to bear upon the concrete article thereby causing the monomer preparation to be diffused into the fine voids in the concrete article, and heating the concrete article in situ thereby allowing the diffused monomer to be polymerized.

摘要翻译： 聚合物浸渍的混凝土产品通过将混凝土混合物放置在能承受高温和高压的框架中以在其中形成中空部分的方式获得，模制混凝土混合物以获得其中含有中空部分的混凝土制品 通过施加热使框架中的密闭状态的混凝土制品保持在紧闭状态，将保持在框架中的混凝土制品进行干燥和脱气处理，然后将单体制剂供应到中空部分 的混凝土制品，施加压力以承受混凝土制品，从而使单体制备物扩散到混凝土制品中的微细空隙中，并对该混凝土制品进行原位加热，从而使扩散的单体聚合。

公开(公告)号：US09418583B2

公开(公告)日：2016-08-16

申请号：US13517462

申请日：2010-12-13

申请人： Seiichi Ozawa ,  Hironobu Akita

发明人： Seiichi Ozawa ,  Hironobu Akita

IPC分类号： G09G5/00 ,  G09G3/20 ,  G09G3/36 ,  H04L25/02

CPC分类号： G09G3/20 ,  G09G3/3611 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2370/08 ,  H04L25/0264

摘要： Reception devices 201 to 20N are arranged one-dimensionally in this order. The reception device 20n has a data input buffer 21, a first clock input buffer 221, and a first clock output buffer 231. The first clock input buffer 221 buffers a clock input to the first clock terminals P21 and P22, and outputs it to the first clock output buffer 231. The first clock output buffer 231 buffers a clock input from the first clock input buffer 221 and outputs it from the second clock terminals P31 and P32. The data input terminals P11 and P12 are located between the first clock terminal and the second clock terminal.

摘要翻译： 接收装置201〜20N依次排列成一维。 接收装置20n具有数据输入缓冲器21，第一时钟输入缓冲器221和第一时钟输出缓冲器231.第一时钟输入缓冲器221缓冲输入到第一时钟端子P21和P22的时钟，并将其输出到 第一时钟输出缓冲器231缓冲从第一时钟输入缓冲器221输入的时钟并将其从第二时钟端子P31和P32输出。 数据输入端子P11和P12位于第一时钟端子和第二时钟端子之间。