公开(公告)号：US09343480B2

公开(公告)日：2016-05-17

申请号：US13197888

申请日：2011-08-04

申请人： Seiichi Yoneda

发明人： Seiichi Yoneda

IPC分类号： H01L27/108 ,  H01L27/12 ,  G11C16/04 ,  H01L27/115 ,  H01L29/786

CPC分类号： H01L27/1225 ,  G11C16/0433 ,  H01L27/11517 ,  H01L27/1251 ,  H01L29/78609 ,  H01L29/7869

摘要： It is an object to give excellent data retention characteristics to a semiconductor device in which stored data is judged in accordance with the potential of a gate of a specified transistor, by achieving both reduction in variation of the threshold voltage of the transistor and data retention for a long time. Charge is held (data is stored) in a node electrically connected only to a source or a drain of a transistor whose channel region is formed using an oxide semiconductor. There may be a plurality of transistors whose sources or drains are electrically connected to the node. The oxide semiconductor has a wider band gap and a lower intrinsic carrier density than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.

摘要翻译： 本发明的目的是通过实现晶体管的阈值电压的变化的减小和数据保持的数据保持以及对于晶体管的阈值电压的变化的降低，对于根据指定晶体管的栅极的电位来判断存储的数据的半导体器件具有优异的数据保持特性 很长时间。 保持电荷（数据被存储）在仅与使用氧化物半导体形成沟道区的晶体管的源极或漏极电连接的节点中。 可以存在多个晶体管，其源极或漏极电连接到节点。 氧化物半导体具有比硅更宽的带隙和更低的本征载流子密度。 通过使用这种氧化物半导体用于晶体管的沟道区域，可以实现具有极低截止电流（漏电流）的晶体管。

公开(公告)号：US09059704B2

公开(公告)日：2015-06-16

申请号：US13477192

申请日：2012-05-22

申请人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

发明人： Seiichi Yoneda ,  Jun Koyama ,  Yutaka Shionoiri ,  Masami Endo ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Kazuaki Ohshima

IPC分类号： G06F1/00 ,  H03K19/177 ,  H03K19/173 ,  G06F3/06

CPC分类号： H03K19/173 ,  G06F1/3243 ,  G06F3/0679 ,  H03K19/17772 ,  Y02D10/152

摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.

摘要翻译： 目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。 可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。 在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

公开(公告)号：US20120037972A1

公开(公告)日：2012-02-16

申请号：US13197888

申请日：2011-08-04

申请人： Seiichi Yoneda

发明人： Seiichi Yoneda

IPC分类号： H01L27/108

CPC分类号： H01L27/1225 ,  G11C16/0433 ,  H01L27/11517 ,  H01L27/1251 ,  H01L29/78609 ,  H01L29/7869

摘要： It is an object to give excellent data retention characteristics to a semiconductor device in which stored data is judged in accordance with the potential of a gate of a specified transistor, by achieving both reduction in variation of the threshold voltage of the transistor and data retention for a long time. Charge is held (data is stored) in a node electrically connected only to a source or a drain of a transistor whose channel region is formed using an oxide semiconductor. There may be a plurality of transistors whose sources or drains are electrically connected to the node. The oxide semiconductor has a wider band gap and a lower intrinsic carrier density than silicon. By using such an oxide semiconductor for the channel region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized.

摘要翻译： 本发明的目的是通过实现晶体管的阈值电压的变化的减小和数据保持的数据保持以及对于晶体管的阈值电压的变化的降低，对于根据指定晶体管的栅极的电位来判断存储的数据的半导体器件具有优异的数据保持特性 很长时间。 保持电荷（数据被存储）在仅与使用氧化物半导体形成沟道区的晶体管的源极或漏极电连接的节点中。 可以存在多个晶体管，其源极或漏极电连接到节点。 氧化物半导体具有比硅更宽的带隙和更低的本征载流子密度。 通过使用这种氧化物半导体用于晶体管的沟道区域，可以实现具有极低截止电流（漏电流）的晶体管。

公开(公告)号：US08664658B2

公开(公告)日：2014-03-04

申请号：US13101266

申请日：2011-05-05

申请人： Seiichi Yoneda

发明人： Seiichi Yoneda

IPC分类号： H01L29/04

CPC分类号： H01L27/1225 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/1214 ,  H01L27/1229 ,  H01L27/1251

摘要： An n-channel transistor or a p-channel transistor provided with a second gate electrode for controlling a threshold voltage in addition to a normal gate electrode is used for a complementary logic circuit. In addition, an insulated gate field-effect transistor with an extremely low off-state current is used as a switching element to control the potential of the second gate electrode. A channel formation region of the transistor which functions as a switching element includes a semiconductor material whose band gap is wider than that of a silicon semiconductor and whose intrinsic carrier density is lower than that of silicon.

摘要翻译： 互补逻辑电路使用n沟道晶体管或p沟道晶体管，该n沟道晶体管或p沟道晶体管具有用于控制除普通栅电极之外的阈值电压的第二栅电极。 此外，使用具有极低截止电流的绝缘栅场效应晶体管作为开关元件来控制第二栅电极的电位。 用作开关元件的晶体管的沟道形成区域包括其带隙比硅半导体的带隙更宽的本征载流子密度低于硅的半导体材料。

公开(公告)号：US08570065B2

公开(公告)日：2013-10-29

申请号：US13437961

申请日：2012-04-03

申请人： Hidetomo Kobayashi ,  Masami Endo ,  Yutaka Shionoiri ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Kazuaki Ohshima ,  Seiichi Yoneda ,  Jun Koyama

发明人： Hidetomo Kobayashi ,  Masami Endo ,  Yutaka Shionoiri ,  Hiroki Dembo ,  Tatsuji Nishijima ,  Kazuaki Ohshima ,  Seiichi Yoneda ,  Jun Koyama

IPC分类号： H03K19/177 ,  G11C11/24

CPC分类号： H03K19/17796 ,  G11C16/0433 ,  H01L27/11803 ,  H01L27/1203

摘要： A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.

摘要翻译： 提供了可以执行动态配置的低功耗可编程LSI。 可编程LSI包括多个逻辑元件。 多个逻辑元件各自包括配置存储器。 多个逻辑元件中的每一个执行不同的运算处理，并且根据存储在配置存储器中的配置数据改变逻辑元件之间的电连接。 配置存储器包括一组易失性存储电路和非易失性存储电路。 非易失性存储电路包括其沟道形成在氧化物半导体层中的晶体管和一对电极中的一个电极与晶体管截止时被设置为浮置状态的节点电连接的电容器。

公开(公告)号：US09041449B2

公开(公告)日：2015-05-26

申请号：US13455195

申请日：2012-04-25

申请人： Seiichi Yoneda ,  Hidetomo Kobayashi

发明人： Seiichi Yoneda ,  Hidetomo Kobayashi

IPC分类号： H03K3/356 ,  H01L27/12 ,  G11C19/18 ,  G11C19/28

CPC分类号： H01L27/1225 ,  G11C19/184 ,  G11C19/28 ,  H03K3/356008

摘要： A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the nonvolatile semiconductor storage device, the volatile storage device and the nonvolatile storage device are provided without separation. Specifically, in the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor.

摘要翻译： 提供一种在不需要在易失性存储装置和非易失性存储装置之间保存和返回数据信号的情况下停止并恢复供电电压的半导体存储装置。 在非易失性半导体存储装置中，不分离地设置易失性存储装置和非易失性存储装置。 具体地，在半导体存储装置中，数据被保持在连接到包括含有氧化物半导体和电容器的半导体层的晶体管的数据保持部分中。 保持在数据保持部分中的数据的电位由数据电位保持电路和数据电位控制电路控制。 数据电位保持电路可以不泄漏电荷而输出数据，并且数据电位控制电路可以通过电容器的电容耦合而不会使电荷泄漏而控制保持在数据保持部分中的数据的电位。

公开(公告)号：US08750058B2

公开(公告)日：2014-06-10

申请号：US13211611

申请日：2011-08-17

申请人： Seiichi Yoneda

发明人： Seiichi Yoneda

IPC分类号： G11C7/00

CPC分类号： G11C29/04 ,  G11C7/1009 ,  G11C29/702

摘要： A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited.

摘要翻译： 提供了一种用于限制将数据写入特定存储器单元而不断开存储单元阵列的布线或将探测器与存储单元，行或列接触的方法。 不能写入数据的存储单元的行地址数据和列地址数据存储在寄存器中。 控制数据写入的数据存储在寄存器中。 接下来，为了将数据写入存储单元，从逻辑电路输出写入数据的存储单元的行地址数据和列地址数据，写使能数据等; 因此，禁止将数据写入与存储在寄存器中的地址数据相对应的存储单元。

公开(公告)号：US08581625B2

公开(公告)日：2013-11-12

申请号：US13463084

申请日：2012-05-03

申请人： Seiichi Yoneda ,  Tatsuji Nishijima

发明人： Seiichi Yoneda ,  Tatsuji Nishijima

IPC分类号： H03K19/173

CPC分类号： H03K19/0013 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869 ,  H03K19/0008 ,  H03K19/17736 ,  H03K19/17744

摘要： An object is to provide a programmable logic device having logic blocks connected to each other by a programmable switch, where the programmable switch is characterized by an oxide semiconductor transistor incorporated therein. The extremely low off-state current of the oxide semiconductor transistor provides a function as a non-volatile memory due to its high ability to hold a potential of a gate electrode of a transistor which is connected to the oxide semiconductor transistor. The ability of the oxide semiconductor transistor to function as a non-volatile memory allows the configuration data for controlling the connection of the logic blocks to be maintained even in the absence of a power supply potential. Hence, the rewriting process of the configuration data at starting of the device can be omitted, which contributes to the reduction in power consumption of the device.

摘要翻译： 目的是提供一种具有通过可编程开关彼此连接的逻辑块的可编程逻辑器件，其中可编程开关的特征在于结合在其中的氧化物半导体晶体管。 氧化物半导体晶体管的非常低的截止电流由于其保持与氧化物半导体晶体管连接的晶体管的栅极的电位的高能力而提供作为非易失性存储器的功能。 氧化物半导体晶体管用作非易失性存储器的能力允许用于控制逻辑块的连接的配置数据即使在没有电源电位的情况下也被维持。 因此，可以省略在设备启动时的配置数据的重写处理，这有助于降低设备的功耗。

公开(公告)号：US20120294066A1

公开(公告)日：2012-11-22

申请号：US13469159

申请日：2012-05-11

申请人： Seiichi Yoneda

发明人： Seiichi Yoneda

IPC分类号： G11C11/24

CPC分类号： H03K3/356008 ,  G11C19/184 ,  G11C19/28

摘要： A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor.

摘要翻译： 提供一种在不需要在易失性存储装置和非易失性存储装置之间保存和返回数据信号的情况下停止并恢复供电电压的半导体存储装置。 在半导体存储装置中，数据被保持在连接到包括含有氧化物半导体和电容器的半导体层的晶体管的数据保持部分中。 保持在数据保持部分中的数据的电位由数据电位保持电路和数据电位控制电路控制。 数据电位保持电路可以不泄漏电荷而输出数据，并且数据电位控制电路可以通过电容器的电容耦合而不会使电荷泄漏而控制保持在数据保持部分中的数据的电位。

公开(公告)号：US20120044778A1

公开(公告)日：2012-02-23

申请号：US13211611

申请日：2011-08-17

申请人： Seiichi Yoneda

发明人： Seiichi Yoneda

IPC分类号： G11C7/00

CPC分类号： G11C29/04 ,  G11C7/1009 ,  G11C29/702

摘要： A method for limiting writing of data to a specific memory cell without disconnecting a wiring of a memory cell array or placing a prober in contact with a memory cell, a row, or a column is provided. Row address data and column address data of a memory cell to which data cannot be written are stored in a register. Enable data which controls data writing is stored in the register. Next, in order to write data to a memory cell, row address data and column address data of a memory cell to which data is written, writing enable data, and the like are output from a logic circuit; thus, writing of data to a memory cell corresponding to the address data stored in the register is inhibited.

摘要翻译： 提供了一种用于限制将数据写入特定存储器单元而不断开存储单元阵列的布线或将探测器与存储单元，行或列接触的方法。 不能写入数据的存储单元的行地址数据和列地址数据存储在寄存器中。 控制数据写入的数据存储在寄存器中。 接下来，为了将数据写入存储单元，从逻辑电路输出写入数据的存储单元的行地址数据和列地址数据，写使能数据等; 因此，禁止将数据写入与存储在寄存器中的地址数据相对应的存储单元。