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    Semiconductor structure
    1.
    发明授权
    Semiconductor structure 有权

    公开(公告)号：US11616064B2

    公开(公告)日：2023-03-28

    申请号：US17019956

    申请日：2020-09-14

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  SMIC New Technology Research and Development (Shanghai) Corporation

    发明人： Yong Li

    IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/84

    摘要： A semiconductor structure is provided. The semiconductor structure includes a base substrate including a semiconductor substrate having a PMOS region and an NMOS region and a plurality of fins on the semiconductor substrate, a gate layer across the plurality of fins by covering portions of top and sidewall surfaces of the fins, a P-type doped epitaxial layer formed in the fins at both sides of the gate layer in the PMOS region, an N-type doped epitaxial layer formed in the fins at both sides of the gate layer in the NMOS region, and an N-region mask layer formed on sidewall surfaces of the N-type doped epitaxial layer and covering the P-type doped epitaxial layer. A portion of the N-type doped epitaxial layer exposed by the N-region mask layer is processed by an N-type dopant segregated Schottky doping process.

    Semiconductor structure and fabrication method thereof
    3.
    发明授权
    Semiconductor structure and fabrication method thereof 有权

    公开(公告)号：US10811414B2

    公开(公告)日：2020-10-20

    申请号：US16106222

    申请日：2018-08-21

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  SMIC New Technology Research and Development (Shanghai) Corporation

    发明人： Yong Li

    IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84

    摘要： Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate including a plurality of fins on a semiconductor substrate; forming a gate layer across the fins; forming a P-type doped epitaxial layer in the fins at both sides of the gate layer in a PMOS region of the semiconductor substrate; forming an N-region mask layer on top and sidewall surfaces of the fins in the NMOS region and covering the P-type doped epitaxial layer; forming an N-region trench; forming an N-type doped epitaxial layer by filling the N-region trench; forming an interlayer dielectric layer over the semiconductor substrate; forming a contact opening to expose the P-type doped epitaxial layer and the N-type doped epitaxial layer; and performing an N-type dopant segregated Schottky (DSS) doping process on a portion of the N-type doped epitaxial layer exposed by the contact opening.

    Static random access memory
    5.
    发明授权
    Static random access memory 有权

    公开(公告)号：US11545496B2

    公开(公告)日：2023-01-03

    申请号：US17032820

    申请日：2020-09-25

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Yong Li

    IPC分类号： H01L29/165 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66 ,  G11C11/412 ,  H01L29/78

    摘要： An SRAM (static random access memory) includes a semiconductor substrate; a plurality of PD transistors, each including a first fin structure formed on the semiconductor substrate, a PD gate structure formed across the first fin structure and covering a portion of a top and sidewall surfaces of the first fin structure, and a first source/drain doped layer formed in the first fin structure on both sides of the PD gate structure; a plurality of adjacent transistors, each including a second fin structure formed on the semiconductor substrate and a second source/drain doped layer formed in the second fin structure; an isolation layer, formed on the semiconductor substrate; a fin sidewall film, formed on the isolation layer and covering sidewall surfaces of each PD gate structure; and a first PD dielectric layer, formed on the isolation layer and covering sidewall surfaces of the first source/drain doped layer.

    Static random-access memory (SRAM) and manufacture thereof
    6.
    发明授权
    Static random-access memory (SRAM) and manufacture thereof 有权

    公开(公告)号：US11152379B2

    公开(公告)日：2021-10-19

    申请号：US16570610

    申请日：2019-09-13

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Yong Li

    IPC分类号： H01L29/06 ,  H01L27/11 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    摘要： A Static Random-Access Memory (SRAM) device and its manufacturing method are presented, relating to semiconductor techniques. The SRAM device includes: a substrate; a first semiconductor column for Pull-Up (PU) transistors and a second semiconductor column for Pull-Down (PD) transistors, with both the first and the second semiconductor columns on the substrate; a first separation region, and a gate stack structure. The first separation region is between the first and the second semiconductor columns and comprises a first region and a second region, the gate stack structure comprises a gate dielectric layer comprising a first part and a second part; a P-type work function regulation layer comprising a first area and a second area adjacent to each other; a N-type work function regulation layer comprising a third area and a fourth area adjacent to each other; and a gate on both the P-type and N-type work function regulation layers.

    Method for fabricating semiconductor device
    7.
    发明授权
    Method for fabricating semiconductor device 有权

    公开(公告)号：US10943912B2

    公开(公告)日：2021-03-09

    申请号：US16403251

    申请日：2019-05-03

    申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

    发明人： Yong Li

    IPC分类号： H01L27/11 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423

    摘要： A semiconductor device includes a base substrate including an NMOS region and a PMOS region. The PMOS region includes a first P-type region and a second P-type region. The semiconductor device also includes an interlayer dielectric layer, a gate structure formed through the interlayer dielectric layer and including an N-type region gate structure formed in the NMOS region, a first gate structure formed in the first P-type region and connected to the N-type region gate structure, and a second gate structure formed in the second P-type region and connected to the first gate structure. The direction from the N-type region gate structure to the second gate structure is an extending direction of the gate structure, and along a direction perpendicular to the extending direction of the gate structure, the width of the first gate structure is larger than the width of the second gate structure.