公开(公告)号：US20060257563A1

公开(公告)日：2006-11-16

申请号：US11329696

申请日：2006-01-11

申请人： Seok-Joo Doh ,  Shi-Woo Rhee ,  Jong-Pyo Kim ,  Jung-Hyoung Lee ,  Jong-Ho Lee ,  Yun-Seok Kim

发明人： Seok-Joo Doh ,  Shi-Woo Rhee ,  Jong-Pyo Kim ,  Jung-Hyoung Lee ,  Jong-Ho Lee ,  Yun-Seok Kim

IPC分类号： C23C16/00

CPC分类号： C23C16/401 ,  C23C16/45529 ,  C23C16/45531

摘要： There are provided methods of fabricating a silicon-doped metal oxide layer on a semiconductor substrate using an atomic layer deposition technique. The methods include an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon-doped metal oxide layer formation cycle Q times. At least one of the values K and Q is an integer of 2 or more. K and Q are integers ranging from 1 to about 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, and then injecting an oxide gas into the reactor. The silicon-doped metal oxide layer formation cycle includes supplying a metal source gas including silicon into a reactor containing the substrate, and then injecting an oxide gas into the reactor. The sequence of operations of repeatedly performing the metal oxide layer formation cycle K times, followed by repeatedly performing the silicon-doped metal oxide layer formation cycle Q times, is performed one or more times until a silicon-doped metal oxide layer with a desired thickness is formed on the substrate. In addition, a method of fabricating a silicon-doped hafnium oxide (Si-doped HfO2) layer according to a similar invention method is also provided.

摘要翻译： 提供了使用原子层沉积技术在半导体衬底上制造掺硅金属氧化物层的方法。 这些方法包括重复进行金属氧化物层形成循环K次的操作和重复进行掺硅金属氧化物层形成循环Q次的操作。 值K和Q中的至少一个是2以上的整数。 K和Q分别为1至约10的整数。 金属氧化物层形成循环包括将金属源气体供给到包含基板的反应器中，然后将氧化物气体注入到反应器中的步骤。 掺杂硅的金属氧化物层形成循环包括将含有硅的金属源气体供给到含有该基板的反应器中，然后将氧化物气体注入反应器。 重复执行金属氧化物层形成循环K次的操作顺序，随后重复进行掺杂硅的金属氧化物层形成循环Q次，执行一次或多次，直到具有所需厚度的掺硅金属氧化物层 形成在基板上。 此外，还提供了根据类似的发明方法制造掺杂硅的氧化铪（Si掺杂的HfO 2 N 2）层的方法。

公开(公告)号：US20060022252A1

公开(公告)日：2006-02-02

申请号：US11193231

申请日：2005-07-29

申请人： Seok-Joo Doh ,  Jong-Pyo Kim ,  Jong-Ho Lee ,  Ki-Chul Kim

发明人： Seok-Joo Doh ,  Jong-Pyo Kim ,  Jong-Ho Lee ,  Ki-Chul Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  H01L29/792

摘要： There are provided a nonvolatile memory device and a method of fabricating the same. A gate region of the nonvolatile memory device is formed as a stack structure including a tunnel oxide layer, a trapping layer, a blocking layer and a control gate electrode. The trapping layer is formed of a high-k dielectric having a higher dielectric constant than that of the tunnel oxide layer. When the trapping layer is formed of high-k dielectric, an EOT in a same thickness can be reduced, and excitation of electrons of the control gate electrode to the tunnel oxide layer due to a high potential barrier relative to the tunnel oxide layer is prevented so that program and erase voltages can be further reduced. As such, a problem that the tunnel oxide layer is damaged due to the conventional high program and erase voltages can be solved by reducing the program and erase voltages, and program and erase speeds of the transistor can be further improved.

摘要翻译： 提供了一种非易失性存储器件及其制造方法。 非易失性存储器件的栅极区域形成为包括隧道氧化物层，俘获层，阻挡层和控制栅电极的堆叠结构。 捕获层由具有比隧道氧化物层的介电常数更高的介电常数的高k电介质形成。 当捕获层由高k电介质形成时，可以减小相同厚度的EOT，并且防止由于相对于隧道氧化物层的高势垒而使控制栅电极的电子激发到隧道氧化物层 从而可以进一步减少编程和擦除电压。 因此，通过减少编程和擦除电压可以解决隧道氧化物层由于常规的高编程和擦除电压而损坏的问题，并且可以进一步提高晶体管的编程和擦除速度。

公开(公告)号：US20050098839A1

公开(公告)日：2005-05-12

申请号：US10930943

申请日：2004-09-01

申请人： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

发明人： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/823857

摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

摘要翻译： 半导体器件包括第一和第二晶体管器件。 第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。 第一栅极电介质位于第一衬底区域和第一栅电极之间。 第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。 第二栅极电介质位于第二基板区域和第二栅极电极之间。 第一栅极电介质包括介电常数为8以上的第一高k层。 类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。 第二高k层具有与第一高k层不同的材料组成。

公开(公告)号：US07586159B2

公开(公告)日：2009-09-08

申请号：US11723705

申请日：2007-03-21

申请人： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

发明人： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

IPC分类号： H01L29/94

CPC分类号： H01L21/823857 ,  H01L27/0922

摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

摘要翻译： 半导体器件包括第一和第二晶体管器件。 第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。 第一栅极电介质位于第一衬底区域和第一栅电极之间。 第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。 第二栅极电介质位于第二基板区域和第二栅极电极之间。 第一栅极电介质包括介电常数为8以上的第一高k层。 类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。 第二高k层具有与第一高k层不同的材料组成。

公开(公告)号：US20070176242A1

公开(公告)日：2007-08-02

申请号：US11723705

申请日：2007-03-21

申请人： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

发明人： Jong-Ho Lee ,  Ho-Kyu Kang ,  Yun-Seok Kim ,  Seok-Joo Doh ,  Hyung-Suk Jung

IPC分类号： H01L29/94

CPC分类号： H01L21/823857 ,  H01L27/0922

摘要： A semiconductor device includes first and second transistor devices. The first device includes a first substrate region, a first gate electrode, and a first gate dielectric. The first gate dielectric is located between the first substrate region and the first gate electrode. The second device includes a second substrate region, a second gate electrode, and a second gate dielectric. The second gate dielectric is located between the second substrate region and the second gate electrode. The first gate dielectric includes a first high-k layer having a dielectric constant of 8 or more. Likewise, the second gate dielectric includes a second high-k layer having a dielectric constant of 8 or more. The second high-k layer has a different material composition than the first high-k layer.

摘要翻译： 半导体器件包括第一和第二晶体管器件。 第一器件包括第一衬底区域，第一栅极电极和第一栅极电介质。 第一栅极电介质位于第一衬底区域和第一栅电极之间。 第二器件包括第二衬底区域，第二栅极电极和第二栅极电介质。 第二栅极电介质位于第二基板区域和第二栅极电极之间。 第一栅极电介质包括介电常数为8以上的第一高k层。 类似地，第二栅极电介质包括介电常数为8或更大的第二高k层。 第二高k层具有与第一高k层不同的材料组成。

公开(公告)号：US20050148127A1

公开(公告)日：2005-07-07

申请号：US10989200

申请日：2004-11-15

申请人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Seok-Joo Doh ,  Yun-Seok Kim

发明人： Hyung-Suk Jung ,  Jong-Ho Lee ,  Seok-Joo Doh ,  Yun-Seok Kim

IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A semiconductor device is disclosed comprising an improved gate dielectric layer formed of a high dielectric alloy-like composite together with a method for fabricating the same. The semiconductor device comprises a semiconductor substrate and a gate dielectric layer consisting essentially of a high-k alloy-like composite containing a first element, a second element, and oxygen (O). The first element is at least one member selected from a first group consisting of Al, La, Y, Ga, and In. The second element is at least one member selected from a second group consisting of Hf, Zr, and Ti. A diffusion barrier is formed on the gate dielectric layer, and a gate is formed on the diffusion barrier.

摘要翻译： 公开了一种半导体器件，其包括由高介电合金样复合材料形成的改进的栅介质层及其制造方法。 半导体器件包括半导体衬底和基本上由含有第一元素，第二元素和氧（O）的高k合金样复合材料组成的栅极电介质层。 第一元素是选自由Al，La，Y，Ga和In组成的第一组中的至少一种。 第二元素是选自由Hf，Zr和Ti构成的第二组中的至少一种。 在栅介电层上形成扩散阻挡层，在扩散阻挡层上形成栅极。

公开(公告)号：US08115262B2

公开(公告)日：2012-02-14

申请号：US12498311

申请日：2009-07-06

申请人： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

发明人： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

IPC分类号： H01L21/02

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/94 ,  Y10T428/265

摘要： A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M′Oy) or amorphous metal oxynitride (M′OyNz).

摘要翻译： 在一个实施例中提供了一种微电子器件的电介质多层结构，其中泄漏电流特性和介电常数得到改善。 电介质多层结构包括由非晶硅酸盐（M1-xSixOy）或无定形硅酸盐氮化物（M1-xSixOyNz）制成的下电介质层，以及形成在下电介质层的顶部上的上电介质层 的无定形金属氧化物（M'Oy）或无定形金属氧氮化物（M'OyNz）。

公开(公告)号：US07588989B2

公开(公告)日：2009-09-15

申请号：US11226053

申请日：2005-09-13

申请人： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

发明人： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/94 ,  Y10T428/265

摘要： A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M′Oy) or amorphous metal oxynitride (M′OyNz).

摘要翻译： 在一个实施例中提供了一种微电子器件的电介质多层结构，其中泄漏电流特性和介电常数得到改善。 电介质多层结构包括由非晶硅酸盐（M1-xSixOy）或无定形硅酸盐氮化物（M1-xSixOyNz）制成的下电介质层，以及形成在下电介质层的顶部上的上电介质层 的无定形金属氧化物（M'Oy）或无定形金属氧氮化物（M'OyNz）。

公开(公告)号：US20060054980A1

公开(公告)日：2006-03-16

申请号：US11226053

申请日：2005-09-13

申请人： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

发明人： Jong-Pyo Kim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Jung-Hyoung Lee

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/28202 ,  H01L21/28185 ,  H01L21/28194 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/94 ,  Y10T428/265

摘要： A dielectric multilayer structure of a microelectronic device, in which a leakage current characteristic and a dielectric constant are improved, is provided in an embodiment. The dielectric multilayer structure includes a lower dielectric layer, which is made of amorphous silicate (M1-xSixOy) or amorphous silicate nitride (M1-xSixOyNz), and an upper dielectric layer which is formed on top of the lower dielectric layer and which is made of amorphous metal oxide (M′Oy) or amorphous metal oxynitride (M′OyNz).

摘要翻译： 在一个实施例中提供了一种微电子器件的电介质多层结构，其中泄漏电流特性和介电常数得到改善。 电介质多层结构包括由非晶态硅酸盐（M 1-x Si x O x O y）或无定形硅酸盐制成的下电介质层 氮化物（M 1-x Si x O y N z N z），以及形成的上电介质层 在下部电介质层的顶部，并且由非晶金属氧化物（M'O y y）或非晶金属氧氮化物（M'O y N y） / SUB>）。

公开(公告)号：US07651729B2

公开(公告)日：2010-01-26

申请号：US11127748

申请日：2005-05-12

申请人： Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

发明人： Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

IPC分类号： C23C16/00

CPC分类号： C23C16/401 ,  C23C16/45529 ,  C23C16/45531

摘要： There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.

摘要翻译： 提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。 所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。 金属硅酸盐层形成循环包括重复进行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。 金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。 氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。