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    Non-volatile memory devices and methods of forming the same
    1.
    发明申请
    Non-volatile memory devices and methods of forming the same 失效
    非易失性存储器件及其形成方法

    公开(公告)号：US20060270156A1

    公开(公告)日：2006-11-30

    申请号：US11246454

    申请日：2005-10-07

    申请人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    发明人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

    摘要翻译： 非易失性存储器件包括设置在衬底上的向上突出的翅片和跨过鳍片的控制栅电极。 浮栅位于控制栅极和鳍之间，并包括第一存储栅和第二存储栅。 第一存储门设置在翅片的侧壁上，第二存储栅极设置在鳍的顶表面上，并连接到第一存储门。 第一绝缘层插入在第一存储栅极和鳍片的侧壁之间，第二绝缘层插入在第二存储栅极和鳍的顶表面之间。 第二绝缘层比第一绝缘层薄。 在控制栅电极和浮栅之间插入阻挡绝缘图案。

    Non-volatile memory devices and methods of forming the same
    2.
    发明授权
    Non-volatile memory devices and methods of forming the same 失效
    非易失性存储器件及其形成方法

    公开(公告)号：US07723188B2

    公开(公告)日：2010-05-25

    申请号：US12274166

    申请日：2008-11-19

    申请人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    发明人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

    摘要翻译： 非易失性存储器件包括设置在衬底上的向上突出的翅片和跨过鳍片的控制栅电极。 浮栅位于控制栅极和鳍之间，并包括第一存储栅和第二存储栅。 第一存储门设置在翅片的侧壁上，第二存储栅极设置在鳍的顶表面上，并连接到第一存储门。 第一绝缘层插入在第一存储栅极和鳍片的侧壁之间，第二绝缘层插入在第二存储栅极和鳍的顶表面之间。 第二绝缘层比第一绝缘层薄。 在控制栅电极和浮栅之间插入阻挡绝缘图案。

    Non-volatile memory devices and methods of forming the same
    3.
    发明授权
    Non-volatile memory devices and methods of forming the same 失效
    非易失性存储器件及其形成方法

    公开(公告)号：US07462904B2

    公开(公告)日：2008-12-09

    申请号：US11246454

    申请日：2005-10-07

    申请人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    发明人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    IPC分类号： H01L29/788

    CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

    摘要翻译： 非易失性存储器件包括设置在衬底上的向上突出的翅片和跨过鳍片的控制栅电极。 浮栅位于控制栅极和鳍之间，并包括第一存储栅和第二存储栅。 第一存储门设置在翅片的侧壁上，第二存储栅极设置在鳍的顶表面上，并连接到第一存储门。 第一绝缘层插入在第一存储栅极和鳍片的侧壁之间，第二绝缘层插入在第二存储栅极和鳍的顶表面之间。 第二绝缘层比第一绝缘层薄。 在控制栅电极和浮栅之间插入阻挡绝缘图案。

    Non-Volatile Memory Devices and Methods of Forming the Same
    4.
    发明申请
    Non-Volatile Memory Devices and Methods of Forming the Same 失效
    非易失性存储器件及其形成方法

    公开(公告)号：US20090081835A1

    公开(公告)日：2009-03-26

    申请号：US12274166

    申请日：2008-11-19

    申请人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    发明人： Seong-Gyun Kim ,  Ji-Hoon Park ,  Sang-Woo Kang ,  Sung-Woo Park

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28273 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

    摘要： A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

    摘要翻译： 非易失性存储器件包括设置在衬底上的向上突出的翅片和跨过鳍片的控制栅电极。 浮栅位于控制栅极和鳍之间，并包括第一存储栅和第二存储栅。 第一存储门设置在翅片的侧壁上，第二存储栅极设置在鳍的顶表面上，并连接到第一存储门。 第一绝缘层插入在第一存储栅极和鳍片的侧壁之间，第二绝缘层插入在第二存储栅极和鳍的顶表面之间。 第二绝缘层比第一绝缘层薄。 在控制栅电极和浮栅之间插入阻挡绝缘图案。

    EEPROM device and manufacturing method thereof
    7.
    发明申请
    EEPROM device and manufacturing method thereof 失效
    EEPROM装置及其制造方法

    公开(公告)号：US20060006452A1

    公开(公告)日：2006-01-12

    申请号：US11087127

    申请日：2005-03-23

    申请人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    发明人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

    摘要翻译： 提供了一种EEPROM器件及其制造方法。 EEPROM装置由包括存储晶体管和位于半导体衬底上的串联选择晶体管的一个单元组成，并且包括位于存储晶体管的侧面区域上的源极区域，位于选择区域的一个侧面区域的漏极区域 面对源极区域的晶体管，以及形成在存储晶体管和选择晶体管之间的浮置结区，其中浮置结区域包括在存储晶体管占据的区域下朝向源极区域延伸的第一掺杂区域和掺杂 其具有与第一掺杂区域相对的导电掺杂剂并且形成为围绕第一掺杂区域。

    EEPROM device having first and second doped regions that increase an effective channel length
    8.
    发明授权
    EEPROM device having first and second doped regions that increase an effective channel length 失效
    具有增加有效沟道长度的第一和第二掺杂区的EEPROM器件

    公开(公告)号：US07408230B2

    公开(公告)日：2008-08-05

    申请号：US11087127

    申请日：2005-03-23

    申请人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    发明人： Ji-Hoon Park ,  Sung-Taeg Kang ,  Seong-Gyun Kim ,  Bo-Young Seo ,  Sung-Woo Park

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/788

    CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    摘要： Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

    摘要翻译： 提供了一种EEPROM器件及其制造方法。 EEPROM装置由包括存储晶体管和位于半导体衬底上的串联选择晶体管的一个单元组成，并且包括位于存储晶体管的侧面区域上的源极区域，位于选择区域的一个侧面区域的漏极区域 面对源极区域的晶体管，以及形成在存储晶体管和选择晶体管之间的浮置结区，其中浮置结区域包括在存储晶体管占据的区域下朝向源极区域延伸的第一掺杂区域和掺杂 其具有与第一掺杂区域相对的导电掺杂剂并且形成为围绕第一掺杂区域。

    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method
    9.
    发明申请
    Method of manufacturing a thin dielectric layer using a heat treatment and a semiconductor device formed using the method 有权
    使用热处理制造薄介电层的方法和使用该方法形成的半导体器件

    公开(公告)号：US20050106897A1

    公开(公告)日：2005-05-19

    申请号：US10832952

    申请日：2004-04-27

    申请人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    发明人： Sung-Taeg Kang ,  Jeong-Uk Han ,  Sung-Woo Park ,  Seung-Beom Yoon ,  Ji-Hoon Park ,  Bo-Young Seo

    IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/314 ,  H01L21/8234 ,  H01L21/44 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/0214 ,  H01L21/02249 ,  H01L21/02252 ,  H01L21/28273 ,  H01L21/3144

    摘要： In a method for forming a semiconductor device and a semiconductor device formed in accordance with the method, a thin dielectric layer is provided between a lower conductive layer and an upper conductive layer. In one embodiment, the thin dielectric layer comprises an inter-gate dielectric layer, the lower conductive layer comprises a floating gate and the upper dielectric layer comprises a control gate of a transistor, for example, a non-volatile memory cell transistor. The thin dielectric layer is formed using a heat treating process that results in reduction of surface roughness of the underlying floating gate, and results in a thin silicon oxy-nitride layer being formed on the floating gate. In this manner, the thin dielectric layer provides for increased capacitive coupling between the lower floating gate and the upper control gate. This also leads to a lowered programming voltage, erasing voltage and read voltage for the transistor, while maintaining the threshold voltage in a desired range. In addition, the size of the transistor and resulting storage cell can be minimized and the need for a high-voltage region in the circuit is mitigated, since, assuming a lowered programming voltage, pumping circuitry is not required.

    摘要翻译： 在根据该方法形成的半导体器件和半导体器件的形成方法中，在下导电层和上导电层之间设置有薄的电介质层。 在一个实施例中，薄介电层包括栅极间电介质层，下导电层包括浮动栅极，上介电层包括晶体管的控制栅极，例如非易失性存储单元晶体管。 使用导致下面的浮置栅极的表面粗糙度降低的热处理工艺形成薄介电层，并且导致在浮动栅极上形成薄的氧氮化硅层。 以这种方式，薄介电层提供在下浮动栅极和上控制栅极之间增加的电容耦合。 这也导致降低的编程电压，擦除晶体管的电压和读取电压，同时将阈值电压保持在期望的范围内。 此外，晶体管和所得到的存储单元的尺寸可以被最小化，并且减轻了对电路中的高电压区域的需要，因为假设降低的编程电压，不需要泵浦电路。