公开(公告)号：US07116255B2

公开(公告)日：2006-10-03

申请号：US11153045

申请日：2005-06-14

申请人： Seung-Chul Lee ,  Kwi-Dong Kim ,  Gyu-Hyun Kim ,  Jong-Ki Kwon ,  Jong-Dae Kim

发明人： Seung-Chul Lee ,  Kwi-Dong Kim ,  Gyu-Hyun Kim ,  Jong-Ki Kwon ,  Jong-Dae Kim

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/1215 ,  H03M1/167 ,  H03M1/804

摘要： A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplifying period, and an amplifier including a first amplifier electrically coupled to the digital to analog converter; a second amplifier electrically coupled to the first amplifier; and a first switch electrically coupled between an input end and an output end of the second amplifier, being turned off during a sampling period, and being turned off during an amplifying period.

公开(公告)号：US20060109154A1

公开(公告)日：2006-05-25

申请号：US11153045

申请日：2005-06-14

申请人： Seung-Chul Lee ,  Kwi-Dong Kim ,  Gyu-Hyun Kim ,  Jong-Ki Kwon ,  Jong-Dae Kim

发明人： Seung-Chul Lee ,  Kwi-Dong Kim ,  Gyu-Hyun Kim ,  Jong-Ki Kwon ,  Jong-Dae Kim

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/1215 ,  H03M1/167 ,  H03M1/804

摘要： A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplifying period, and an amplifier including a first amplifier electrically coupled to the digital to analog converter; a second amplifier electrically coupled to the first amplifier; and a first switch electrically coupled between an input end and an output end of the second amplifier, being turned off during a sampling period, and being turned off during an amplifying period.

摘要翻译： 一种乘法数模转换器，包括具有并联耦合的多个电容器的数模转换器，在采样周期期间将第一信号施加到电容器，以及在放大期间向电容器施加第二信号，以及放大器，包括第一 放大器电耦合到数模转换器; 电耦合到所述第一放大器的第二放大器; 并且电耦合在第二放大器的输入端和输出端之间的第一开关在采样周期期间被关断，并且在放大期间被关断。

公开(公告)号：US20110235452A1

公开(公告)日：2011-09-29

申请号：US12814702

申请日：2010-06-14

申请人： Kwi-Dong Kim ,  Ki-Chang Kwean

发明人： Kwi-Dong Kim ,  Ki-Chang Kwean

IPC分类号： G11C17/16

CPC分类号： G11C16/16 ,  G11C16/18

摘要： A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information.

摘要翻译： 一种半导体存储器件，包括：信息存储单元，包括被配置为存储信息的熔丝;控制单元，被配置为响应于控制脉冲信号控制熔断熔丝的节点变为浮置状态;以及输出单元， 信息。

公开(公告)号：US07916560B2

公开(公告)日：2011-03-29

申请号：US12165171

申请日：2008-06-30

申请人： Kwi-Dong Kim

发明人： Kwi-Dong Kim

IPC分类号： G11C7/00

CPC分类号： G11C29/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/025 ,  G11C29/50008 ,  G11C2207/2254

摘要： A semiconductor memory device can determine whether control for supplying termination resistances is normally performed or not by applying a test signal. The device includes a termination resistance driving controller configured to receive a plurality of termination resistance setting signals in synchronization with an external clock and a delay locked loop (DLL) clock to output a plurality of pre-driving signals and a plurality of termination resistance driving signals for a predetermined time. A data pre-driver is configured to output data in synchronization with the external clock. A test driving detector is configured to drive output nodes to a predetermined voltage level in response to a test signal and the plurality of pre-driving signals. A data output buffer is configured to apply termination resistances corresponding to the plurality of termination resistance driving signals to input/output pads, and output the data from the output nodes to the input/output pads.

摘要翻译： 半导体存储器件可以通过施加测试信号来确定是否正常执行用于提供终端电阻的控制。 该装置包括终端电阻驱动控制器，其被配置为与外部时钟和延迟锁定环（DLL）时钟同步地接收多个终端电阻设置信号，以输出多个预驱动信号和多个终端电阻驱动信号 预定时间。 数据预驱动器被配置为与外部时钟同步地输出数据。 测试驱动检测器被配置为响应于测试信号和多个预驱动信号而将输出节点驱动到预定电压电平。 数据输出缓冲器被配置为将对应于多个终端电阻驱动信号的终止电阻施加到输入/输出焊盘，并将数据从输出节点输出到输入/输出焊盘。

公开(公告)号：US20130279279A1

公开(公告)日：2013-10-24

申请号：US13595615

申请日：2012-08-27

申请人： Kwi-Dong Kim

发明人： Kwi-Dong Kim

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A semiconductor device includes a fuse unit connected to a detection node and configured to be programmed in response to a first voltage supplied through the detection node, an output unit connected to the detection node and configured to output a fuse information signal indicating whether the fuse unit is programmed or not, and a blocking unit configured to block the first voltage supplied through the detection node in response to the fuse information signal.

摘要翻译： 半导体器件包括连接到检测节点并被配置为响应于通过检测节点提供的第一电压被编程的熔丝单元，连接到检测节点的输出单元，并且被配置为输出指示熔丝单元 被配置为阻止响应于熔丝信息信号通过检测节点提供的第一电压的阻塞单元。

公开(公告)号：US08248872B2

公开(公告)日：2012-08-21

申请号：US12881693

申请日：2010-09-14

申请人： Kwi-Dong Kim

发明人： Kwi-Dong Kim

IPC分类号： G11C7/00

CPC分类号： G11C29/24 ,  G11C29/50012 ,  G11C29/78

摘要： A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy memory cell corresponding to the external address to be accessed in response to the repair control signal and an internal active signal, and an activation interval detection unit configured to generate an interval detection signal by detecting a time interval between an activation timing of the repair control signal and an activation timing of the internal active signal in a test operation mode.

摘要翻译： 半导体存储器件包括：修复控制信号生成单元，被配置为将对应于修复对象存储单元编程的修复对象地址与外部地址进行比较，并生成修复控制信号。 地址解码单元，被配置为响应于所述修复控制信号和内部有效信号来控制与要访问的外部地址相对应的正常存储单元或冗余存储单元，以及激活间隔检测单元，被配置为产生间隔检测信号 通过在测试操作模式中检测修复控制信号的激活定时和内部有效信号的激活定时之间的时间间隔。

公开(公告)号：US08134879B2

公开(公告)日：2012-03-13

申请号：US12326537

申请日：2008-12-02

申请人： Kwi-Dong Kim

发明人： Kwi-Dong Kim

IPC分类号： G11C7/00

CPC分类号： G11C5/025 ,  G11C29/785

摘要： A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input.

摘要翻译： 一种半导体存储器件包括一组单位单元，其中两个或更多个相邻的单元组共享一冗余电路，该冗余电路被配置为当输入用于访问缺陷单位单元的地址时执行缺陷修复操作。

公开(公告)号：US08120973B2

公开(公告)日：2012-02-21

申请号：US12487181

申请日：2009-06-18

申请人： Mun-Phil Park ,  Kwi-Dong Kim ,  Sung-Ho Kim

发明人： Mun-Phil Park ,  Kwi-Dong Kim ,  Sung-Ho Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C8/08

摘要： A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals.

摘要翻译： 半导体存储器件包括第一存储器组和第二存储器组以及公共写入驱动器，其被配置为将写入数据驱动到第一存储器组和第二存储器组的激活存储器组。 半导体存储器件的公共写入驱动器包括：公共写入控制块，被配置为产生与写入数据相对应的公共驱动控制信号，以及公共写入驱动块，被配置为驱动第一存储体的传输线或第二存储器的传输线 存储体，其响应于公共驱动控制信号由存储体选择信号选择。

公开(公告)号：US09142319B2

公开(公告)日：2015-09-22

申请号：US13595615

申请日：2012-08-27

申请人： Kwi-Dong Kim

发明人： Kwi-Dong Kim

IPC分类号： G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A semiconductor device includes a fuse unit connected to a detection node and configured to be programmed in response to a first voltage supplied through the detection node, an output unit connected to the detection node and configured to output a fuse information signal indicating whether the fuse unit is programmed or not, and a blocking unit configured to block the first voltage supplied through the detection node in response to the fuse information signal.

摘要翻译： 半导体器件包括连接到检测节点并被配置为响应于通过检测节点提供的第一电压被编程的熔丝单元，连接到检测节点的输出单元，并且被配置为输出指示熔丝单元 被配置为阻止响应于熔丝信息信号通过检测节点提供的第一电压的阻塞单元。

公开(公告)号：US08634265B2

公开(公告)日：2014-01-21

申请号：US12814702

申请日：2010-06-14

申请人： Kwi-Dong Kim ,  Ki-Chang Kwean

发明人： Kwi-Dong Kim ,  Ki-Chang Kwean

IPC分类号： G11C17/18

CPC分类号： G11C16/16 ,  G11C16/18

摘要： A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information.

摘要翻译： 一种半导体存储器件，包括：信息存储单元，包括被配置为存储信息的熔丝;控制单元，被配置为响应于控制脉冲信号控制熔断熔丝的节点变为浮置状态;以及输出单元， 信息。