公开(公告)号：US06469558B1

公开(公告)日：2002-10-22

申请号：US09558460

申请日：2000-04-25

申请人： Shad R. Shepston ,  M. Jason Welch

发明人： Shad R. Shepston ,  M. Jason Welch

IPC分类号： H03H1126

CPC分类号： H03K5/133 ,  H03K5/08 ,  H03K2005/00058

摘要： A voltage ramp/threshold variable pulse delay circuit implemented on an IC varies the R instead of the C, which may be fixed. A variable R is formed by a plurality of FET's arranged in parallel. The FET's are sized according to a weighting scheme, which may be binary, and the amount of R produced is determined by which combination of FET's is switched ON, rather than by analog variations in their drive level. If the plurality of sized parallel FET's is made up of individual FET's all of the same polarity, then an undesirable reduction in voltage comparison range will obtain, which may produce an objectionable reduction in available pulse delay if VDD is reduced such that it is no longer many times larger than FET threshold voltage. That reduction in voltage comparison range can be eliminated by replacing each such individual FET with a pair of similarly sized FET's in parallel, the members of which pair are of opposite polarities. The additional FET's have their own drive signals that correspond to the original drive signals.

摘要翻译： 在IC上实现的电压斜坡/阈值可变脉冲延迟电路改变R而不是可以固定的C。 变量R由并排布置的多个FET形成。 根据加权方案，FET的尺寸可以是二进制的，并且产生的R R的量由FET的组合被接通而不是其驱动电平的模拟变化来确定。 如果多个大小的并联FET由相同极性的单个FET组成，则电压比较范围将不利地减小，如果VDD被减小，则可能产生令人不快的可用脉冲延迟降低 比FET阈值电压多很多倍。 可以通过用一对类似尺寸的FET并联来替换每个这样的单个FET来消除电压比较范围的减小，其中成对具有相反的极性。 额外的FET具有与原始驱动信号对应的自己的驱动信号。

公开(公告)号：US06741946B2

公开(公告)日：2004-05-25

申请号：US10383323

申请日：2003-03-07

申请人： John G. Rohrbaugh ,  Jeffrey R. Rearick ,  Shad R. Shepston

发明人： John G. Rohrbaugh ,  Jeffrey R. Rearick ,  Shad R. Shepston

IPC分类号： G01R313187

CPC分类号： G01R31/3187

摘要： A preferred system for facilitating automated test equipment functionality within integrated circuits includes automated test equipment (ATE) configured to electrically interconnect with an integrated circuit and to provide at least one signal to the integrated circuit. A first parametric test circuit, internal to the integrated circuit, also is provided. The first parametric test circuit is adapted to electrically communicate with the automated test equipment so that, in response to receiving a signal from the automated test equipment, the first parametric test circuit measures at least one parameter of a first pad of the integrated circuit.

摘要翻译： 用于促进集成电路内的自动测试设备功能的优选系统包括被配置为与集成电路电互连并且向集成电路提供至少一个信号的自动测试设备（ATE）。 还提供了集成电路内部的第一参数测试电路。 第一参数测试电路适于与自动测试设备电通信，使得响应于接收到来自自动测试设备的信号，第一参数测试电路测量集成电路的第一焊盘的至少一个参数。

公开(公告)号：US06396312B1

公开(公告)日：2002-05-28

申请号：US09637534

申请日：2000-08-11

申请人： Shad R. Shepston ,  Jeff Rearick ,  John G Rohrbaugh

发明人： Shad R. Shepston ,  Jeff Rearick ,  John G Rohrbaugh

IPC分类号： H03B2100

CPC分类号： G04F10/04

摘要： A gate transition counter. A ring oscillator provides a plurality outputs, each delayed from the adjacent output by a gate delay. The outputs of the ring oscillator are captured by an array of latches upon receipt of a halt signal. The last latch drives a ripple counter. The preferred implementation uses five inverters in the ring oscillator so that each complete cycle of the ring oscillator represents ten gate delays. A ripple counter counts the number of gate delays by ten. The latch outputs and the ripple counter outputs can be converted to a binary representation of the number of gate delays to provide a count with the smallest time increment that can be produced by the circuit.

摘要翻译： 门过渡计数器。 环形振荡器提供多个输出，每个输出通过门延迟从相邻输出延迟。 在收到停止信号时，环形振荡器的输出由锁存器阵列捕获。 最后一个锁存器驱动纹波计数器。 优选的实施方案在环形振荡器中使用五个反相器，使得环形振荡器的每个完整周期表示十个门延迟。 纹波计数器将门延迟数量计数为十。 锁存器输出和纹波计数器输出可以转换为门延迟数的二进制表示，以提供可由电路产生的最小时间增量的计数。

公开(公告)号：US06556938B1

公开(公告)日：2003-04-29

申请号：US09649797

申请日：2000-08-29

申请人： John G. Rohrbaugh ,  Jeffrey R. Rearick ,  Shad R. Shepston

发明人： John G. Rohrbaugh ,  Jeffrey R. Rearick ,  Shad R. Shepston

IPC分类号： G01R313187

CPC分类号： G01R31/3187

摘要： A preferred system for facilitating automated test equipment functionality within integrated circuits includes automated test equipment (ATE) configured to electrically interconnect with an integrated circuit and to provide at least one signal to the integrated circuit. A first parametric test circuit, internal to the integrated circuit, also is provided. The first parametric test circuit is adapted to electrically communicate with the automated test equipment so that, in response to receiving a signal from the automated test equipment, the first parametric test circuit measures at least one parameter of a first pad of the integrated circuit.

摘要翻译： 用于促进集成电路内的自动测试设备功能的优选系统包括被配置为与集成电路电互连并且向集成电路提供至少一个信号的自动测试设备（ATE）。 还提供了集成电路内部的第一参数测试电路。 第一参数测试电路适于与自动测试设备电通信，使得响应于接收到来自自动测试设备的信号，第一参数测试电路测量集成电路的第一焊盘的至少一个参数。

公开(公告)号：US6094089A

公开(公告)日：2000-07-25

申请号：US036035

申请日：1998-03-06

申请人： Shad R. Shepston

发明人： Shad R. Shepston

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/088 ,  H03K19/003 ,  H03K3/01

CPC分类号： H03K19/00361 ,  H03K19/00315 ,  H01L2924/0002

摘要： The inventive mechanism prevents current flow from the drain to the source and substrate, in a power off condition of a p-type FET. The current flow from the drain to the substrate is prevented by raising the voltage required to turn on the diodes that are formed when the power is off. This is accomplished by having the substrate gate connected to a series of diodes formed from other pFET devices. The combined threshold voltage of the series exceeds a voltage associated with the current. The current flow from the drain to the source is prevented by pinching off the channel of the pFET during a power off condition. Since a high signal is required to turn off a pFET device and the power to the pFET is off, an off chip voltage associated with the current is used to turn off the pFET. A current sink FET is used to prevent reflections by supplying the proper impedance to receive the off chip signal associated with the current.

摘要翻译： 在p型FET的电源关闭状态下，本发明的机构防止电流从漏极流到源极和衬底。 通过提高打开在电源关闭时形成的二极管所需的电压来防止从漏极到衬底的电流。 这通过使衬底栅极连接到由其它pFET器件形成的一系列二极管来实现。 串联的组合阈值电压超过与电流相关的电压。 在断电状态下，通过夹持pFET的沟道来防止从漏极到源极的电流。 由于需要高信号来关闭pFET器件并且pFET的电源关闭，所以使用与电流相关的芯片外电压来关断pFET。 电流吸收FET用于通过提供适当的阻抗来接收与电流相关联的关断信号来防止反射。

公开(公告)号：US08181125B2

公开(公告)日：2012-05-15

申请号：US10212360

申请日：2002-08-05

申请人： Jason Harold Culler ,  Shad R. Shepston

发明人： Jason Harold Culler ,  Shad R. Shepston

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A system and method for providing compliant mapping between chip bond locations of an IC and corresponding package bond locations is disclosed. Package design information including package bond location information relating to the IC package and IC mask data including chip bond location information relating to the IC chip are integrated such that an internal physical design verification tool is operable to verify compliance between package bond locations and chip bond locations.

摘要翻译： 公开了一种用于在IC的芯片接合位置和相应的封装焊接位置之间提供兼容映射的系统和方法。 包括与IC封装相关的封装焊接位置信息和包括与IC芯片相关的芯片焊接位置信息的IC掩模数据的封装设计信息被集成，使得内部物理设计验证工具可操作以验证封装焊接位置和芯片焊接位置之间的兼容性 。

公开(公告)号：US06907376B2

公开(公告)日：2005-06-14

申请号：US10383668

申请日：2003-03-07

申请人： Shad R. Shepston ,  Jeffrey R. Rearick ,  John G. Rohrbaugh

发明人： Shad R. Shepston ,  Jeffrey R. Rearick ,  John G. Rohrbaugh

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/32

CPC分类号： G01R31/3183

摘要： A preferred integrated circuit for facilitating receiver trip level testing functionality includes a first pad which incorporates a first driver and a first receiver. The first driver is configured to provide a first pad output signal to a component external to the IC. The first receiver is configured to receive a first pad input signal from a component external to the IC, and to provide a first receiver digital output signal to a component internal to the IC in response to the first pad input signal. Additionally, a first test circuit is provided that is arranged internal to the IC, with the first test circuit being adapted to provide information corresponding to at least one receiver trip-level characteristic of the first receiver of the first pad. Systems, methods and computer readable media also are provided.

摘要翻译： 用于促进接收机跳闸电平测试功能的优选集成电路包括包含第一驱动器和第一接收器的第一焊盘。 第一驱动器被配置为向IC外部的部件提供第一焊盘输出信号。 第一接收器被配置为从IC外部的部件接收第一焊盘输入信号，并且响应于第一焊盘输入信号向IC内部的部件提供第一接收器数字输出信号。 此外，提供了布置在IC内部的第一测试电路，其中第一测试电路适于提供对应于第一焊盘的第一接收器的至少一个接收器跳闸电平特性的信息。 还提供了系统，方法和计算机可读介质。

公开(公告)号：US06577980B1

公开(公告)日：2003-06-10

申请号：US09723831

申请日：2000-11-28

申请人： Shad R. Shepston ,  Jeffrey R. Rearick ,  John G. Rohrbaugh

发明人： Shad R. Shepston ,  Jeffrey R. Rearick ,  John G. Rohrbaugh

IPC分类号： G06F1130

CPC分类号： G01R31/3183

摘要： A preferred integrated circuit for facilitating receiver trip level testing functionality includes a first pad which incorporates a first driver and a first receiver. The first driver is configured to provide a first pad output signal to a component external to the IC. The first receiver is configured to receive a first pad input signal from a component external to the IC, and to provide a first receiver digital output signal to a component internal to the IC in response to the first pad input signal. Additionally, a first test circuit is provided that is arranged internal to the IC, with the first test circuit being adapted to provide information corresponding to at least one receiver trip-level characteristic of the first receiver of the first pad. Systems, methods and computer readable media also are provided.

公开(公告)号：US06181185B2

公开(公告)日：2001-01-30

申请号：US09357340

申请日：1999-07-14

申请人： Shad R. Shepston

发明人： Shad R. Shepston

IPC分类号： H03K300

CPC分类号： H03K5/151

摘要： Two complementary clocks that are well matched are produced from a single input clock. A clock buffer includes an alternating series of edge-rate-controlled inverters and level restoring inverters. The output of this series of inverters is compared to the input clock by a race timer. If the output of the series of inverters switches in the opposite direction before the input clock, the edge rates of the series of inverters are slowed down. If the output of the series of inverters switches in the opposite direction after the input clock, the edge rates of the series of inverters are speeded up. The output of the series of inverters eventually approaches the timing of the input clock but complemented. These signals form a pair of complementary clocks with well matched timing.

摘要翻译： 两个完全匹配的互补时钟由单个输入时钟产生。 时钟缓冲器包括一系列边缘速率控制的逆变器和电平恢复逆变器。 该系列逆变器的输出通过比赛定时器与输入时钟进行比较。 如果一系列逆变器的输出在输入时钟之前以相反的方向切换，则一系列逆变器的边沿速率变慢。 如果一系列逆变器的输出在输入时钟之后相反方向切换，则系列逆变器的边沿速率将加快。 该系列逆变器的输出最终接近输入时钟的时序，但相辅相成。 这些信号形成一对具有良好匹配定时的互补时钟。

公开(公告)号：US07746924B2

公开(公告)日：2010-06-29

申请号：US11430692

申请日：2006-05-09

申请人： Karl Joseph Bois ,  Dacheng Zhou ,  Shad R. Shepston ,  David W. Quint

发明人： Karl Joseph Bois ,  Dacheng Zhou ,  Shad R. Shepston ,  David W. Quint

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H03H21/0027

摘要： For a given channel and a filter having at least one filter tap, a set of at least one weight value is determined for the at least one filter tap according to which at least one weight value substantially minimizes a gradient of a frequency response for the given channel and substantially maximizes energy of the frequency response for the given channel within a predetermined bandwidth.

摘要翻译： 对于给定的信道和具有至少一个滤波器抽头的滤波器，确定至少一个滤波器滤波器的至少一个权重值的集合，根据该滤波器抽头，至少一个权重值基本上使给定的频率响应的梯度最小化 并且在预定带宽内基本上最大化给定信道的频率响应的能量。