公开(公告)号：US5723355A

公开(公告)日：1998-03-03

申请号：US785234

申请日：1997-01-17

申请人： Shang-De Ted Chang ,  Binh Ly

发明人： Shang-De Ted Chang ,  Binh Ly

IPC分类号： H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/11546 ,  H01L27/105

摘要： A semiconductor fabrication process allows for the fabrication of high-voltage transistors, logic transistors, and memory cells where, as required for sub-0.3 micron device geometries, the gate oxide of the logic transistors is thinner than the tunnel oxide thickness of the non-volatile memory cells without the undesirable contamination of the gate oxide of the logic transistors or contamination of the tunnel oxide of the memory cells. In one embodiment, the tunnel oxide of the memory cells is grown to a desired thickness. In a next step, a layer of doped polysilicon which will serve as the floating gate of the memory cell(s) is immediately deposited over the tunnel oxide of the memory cells, thereby protecting the tunnel oxide from contamination in subsequent masking and etching steps. The gate oxide of the logic transistors and the gate oxide of the high-voltage transistors are then grown to a desired thickness.

摘要翻译： 半导体制造工艺允许制造高压晶体管，逻辑晶体管和存储器单元，其中，如亚0.3微米器件几何形状所要求的，逻辑晶体管的栅极氧化物比非晶体管的隧道氧化物厚度薄， 非易失性存储单元，而不会对逻辑晶体管的栅极氧化物的不期望的污染或者存储单元的隧道氧化物的污染。 在一个实施例中，将存储器单元的隧道氧化物生长至期望的厚度。 在下一步骤中，将作为存储器单元的浮置栅极的掺杂多晶硅层立即沉积在存储器单元的隧道氧化物上，从而在随后的掩模和蚀刻步骤中保护隧道氧化物免受污染。 然后将逻辑晶体管的栅极氧化物和高电压晶体管的栅极氧化物生长至期望的厚度。

公开(公告)号：US5841165A

公开(公告)日：1998-11-24

申请号：US577405

申请日：1995-12-22

申请人： Shang-De Ted Chang ,  Jayson Giai Trinh

发明人： Shang-De Ted Chang ,  Jayson Giai Trinh

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883 ,  H01L29/7885

摘要： A P-channel single-poly EPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel and, in some embodiments, over significant portions of P+ source and P+ drain regions. A poly-silicon floating gate overlies the tunnel oxide. A P diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. In this manner, the P diffusion region serves as a control gate for the memory cell. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions to cause the hot injection of electrons from the N-well/drain junction to the floating gate, while erasing is realized by biasing the floating gate, N-well, source and drain regions appropriately so as cause the tunneling of electrons from the floating gate to the N-well, the source, and the drain. In another embodiment, an N-type diffusion region is formed within the P diffusion region and serves as the control gate.

公开(公告)号：US5687118A

公开(公告)日：1997-11-11

申请号：US557589

申请日：1995-11-14

申请人： Shang-De Ted Chang

发明人： Shang-De Ted Chang

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11536 ,  H01L29/7885

摘要： A P-channel MOS memory cell has P+ source and drain regions formed in an N-well. A thin tunnel oxide is provided between the well surface and an overlying floating gate. In one embodiment, the thin tunnel oxide extends over a substantial portion of the active region and the device. An overlying control gate is insulated from the floating gate by an insulating layer. The device is programmed via hot electron injection from the drain end of the channel region to the floating gate, without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate to the N-well with the source, drain, and N-well regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

摘要翻译： P沟道MOS存储单元具有形成在N阱中的P +源极和漏极区。 在井表面和上浮动门之间提供薄隧道氧化物。 在一个实施例中，薄隧道氧化物在有源区域和器件的大部分上延伸。 上覆控制栅极通过绝缘层与浮动栅极绝缘。 通过从通道区域的漏极端到浮动栅极的热电子注入来对器件进行编程，而不会产生雪崩击穿，从而允许在编程期间对单元进行位选择。 通过从浮置栅极到N阱的电子隧穿实现擦除，源极，漏极和N阱区域均匀偏置。 由于没有高的漏/阱结偏置电压，可以减少电池的通道长度，而不会产生和破坏性结应力。

公开(公告)号：US5666307A

公开(公告)日：1997-09-09

申请号：US557514

申请日：1995-11-14

申请人： Shang-De Ted Chang

发明人： Shang-De Ted Chang

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0433 ,  H01L27/115 ,  H01L29/7881 ,  H01L29/7887

摘要： A P-channel flash EEPROM cell has P+ source and P+ drain regions, and a channel extending therebetween, formed in an N-type well. A thin layer of tunnel oxide is provided over the channel. A poly-silicon floating gate and poly-silicon control gate, separated by a dielectric layer, overlie the tunnel oxide. Programming is accomplished via hot electron injection while erasing is realized by electron tunneling. The threshold voltage of the cell may be precisely controlled by the magnitude of voltage coupled to the floating gate during programming. Since the injection of hot electrons into the floating gate is independent of variations in the thickness of the tunnel oxide layer and the coupling ratio between the floating gate and the control gate, programming operations and data retention are not affected by process variations. In addition, PMOS devices conduct a gate current via hot electron injection over a narrow range of gate voltages, thereby allowing for precise control over the gate current and thus over the charging of the floating gate. This control over the gate current, as well as the independence of the cell's threshold voltage of process parameters, advantageously allows the threshold voltage of the cell to be more accurately controlled, thereby resulting in a more reliable cell capable of storing a greater number of bits of data.

摘要翻译： P沟道快闪EEPROM单元具有P +源极和P +漏极区域以及在其间延伸的沟道，形成在N型阱中。 在通道上提供了一层隧道氧化物。 由电介质层分离的多晶硅浮栅和多晶硅控制栅极覆盖隧道氧化物。 通过热电子注入实现编程，同时通过电子隧道实现擦除。 可以通过在编程期间耦合到浮动栅极的电压的幅度精确地控制单元的阈值电压。 由于将热电子注入到浮动栅极中与隧道氧化物层的厚度变化和浮动栅极与控制栅极之间的耦合比无关，所以编程操作和数据保持不受过程变化的影响。 此外，PMOS器件通过在窄范围的栅极电压上的热电子注入导通栅极电流，从而允许对栅极电流的精确控制，从而允许精确地控制浮置栅极的充电。 对栅极电流的这种控制以及电池的工艺参数的阈值电压的独立性有利地允许更精确地控制电池的阈值电压，从而导致更可靠的电池能够存储更多数量的位 数据的。

公开(公告)号：US07078761B2

公开(公告)日：2006-07-18

申请号：US10794564

申请日：2004-03-05

申请人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

发明人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

摘要： A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

摘要翻译： 用于多次编程应用的单多晶双晶体管PMOS存储器单元包括共享漏极/源极P +扩散区的PMOS浮栅晶体管，其中PMOS选择栅晶体管全部形成在第一n阱内。 用于浮栅晶体管的控制板形成在第二n阱中。 用于一次编程应用的单晶双转移器PMOS存储器单元包括具有在单个n阱中形成为p +扩散区的源的PMOS浮栅晶体管。 源极也适用于浮栅晶体管的控制板。

公开(公告)号：US5912842A

公开(公告)日：1999-06-15

申请号：US947850

申请日：1997-10-09

申请人： Shang-De Ted Chang ,  Vikram Kowshik ,  Andy Teng Feng Yu ,  Nader Radjy

发明人： Shang-De Ted Chang ,  Vikram Kowshik ,  Andy Teng Feng Yu ,  Nader Radjy

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/0416 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L29/7885

摘要： A nonvolatile memory array is disclosed which includes a plurality of PMOS two-transistor (2T) memory cells. Each 2T cell includes a PMOS floating gate transistor and a PMOS select transistor and is connected between a bit line and a common source line. The select gate and the control gate of each 2T cell in a common row are connected to a word line and to a control gate line, respectively. The 2T cells of the array are programmed using a combination of FN tunneling and BTBT induced hot electron injection, and are erased using FN tunneling. In some embodiments, the array is divided into sectors, where each sector is defined by an n- well region and includes a predetermined number of rows of the 2T cells. Here, the source of each 2T cell in a sector is coupled to a common source line of the sector. In other embodiments, the bit lines of the array are segmented along sector boundaries.

摘要翻译： 公开了一种非易失性存储器阵列，其包括多个PMOS双晶体管（2T）存储单元。 每个2T单元包括PMOS浮栅晶体管和PMOS选择晶体管，并且连接在位线和公共源极线之间。 公共行中的每个2T单元的选择栅极和控制栅极分别连接到字线和控制栅极线。 使用FN隧穿和BTBT诱导的热电子注入的组合对阵列的2T电池进行编程，并使用FN隧道擦除。 在一些实施例中，阵列被划分为扇区，其中每个扇区由n-阱区域定义并且包括预定数量的2T个单元的行。 这里，扇区中的每个2T单元的源耦合到扇区的公共源线。 在其他实施例中，阵列的位线沿着扇区边界被分段。

公开(公告)号：US5801994A

公开(公告)日：1998-09-01

申请号：US911968

申请日：1997-08-15

申请人： Shang-De Ted Chang ,  Chinh D. Nguyen ,  Guy S. Yuen

发明人： Shang-De Ted Chang ,  Chinh D. Nguyen ,  Guy S. Yuen

IPC分类号： G11C16/04

CPC分类号： G11C16/0416

摘要： A memory array includes a predetermined number of rows of PMOS Flash memory cells formed in each of a plurality of n- well regions of a semiconductor substrate, where each of the n- well regions defines a page of the memory array. In some embodiments, a plurality of bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the bit lines. In other embodiments, a plurality of sub-bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the sub-bit lines, and groups of a predetermined number of the sub-bit lines are selectively coupled to associated ones of a plurality of bit lines via pass transistors. During erasing operations a selected n- well region, within which are formed the memory cells of a selected page, is held at a first voltage, while the other n- well regions, within which are formed the memory cells of the respective un-selected pages, are held at a second voltage. The first and second voltages are different, thereby isolating the un-selected pages from erasing operations of the selected page.

摘要翻译： 存储器阵列包括形成在半导体衬底的多个n阱区域中的每一个中的预定数量的PMOS闪存单元行，其中n阱区域中的每一个限定存储器阵列的页面。 在一些实施例中，多个位线限定存储器阵列的列，其中公共列中的每个存储器单元的p +漏极耦合到相关联的一个位线。 在其他实施例中，多个子位线定义存储器阵列的列，其中公共列中的每个存储器单元的p +漏极耦合到相关联的一个子位线，以及预定的 子位线的数量通过传输晶体管选择性地耦合到多个位线中的相关联的位线。 在擦除操作期间，形成所选页面的存储单元的选定n阱区域被保持在第一电压，而在其中形成相应未选择的存储单元的其它n-阱区域 页面被保持在第二电压。 第一和第二电压是不同的，从而将未选择的页面与所选页面的擦除操作隔离。

公开(公告)号：US5761121A

公开(公告)日：1998-06-02

申请号：US744699

申请日：1996-10-31

申请人： Shang-De Ted Chang

发明人： Shang-De Ted Chang

IPC分类号： H01L27/115 ,  H01L29/788 ,  G11C11/34

CPC分类号： H01L27/115 ,  H01L29/7883 ,  H01L29/7885

摘要： A P-channel single-poly non-volatile memory cell having P+ source and P+ drain regions and a channel extending therebetween is formed in an N-type well. An overlying poly-silicon floating gate is separated from the N-well by a thin oxide layer. A P-type diffusion region is formed in a portion of the N-well underlying the floating gate and is thereby capacitively coupled to the floating gate. Within this P-type diffusion area lies an N-type diffusion area which serves as the control gate for the cell. The P-type diffusion region electrically isolates the control gate from the N-well such that voltages may be applied to the control gate in excess of those applied to the N-well without creating a current path from the control gate to the N-well. Programming is accomplished by coupling a sufficient voltage to the floating gate via the control gate while biasing the source and drain regions so as to cause the tunneling of electrons from the P+ drain region of the cell to the floating gate. In some embodiments, an additional P-type diffusion region underlying the floating gate and separated therefrom by a layer of tunnel oxide serve as an erase gate for the memory cell. In such embodiments, erasing of the cell is accomplished by causing electrons to tunnel from the floating gate to the erase gate.

摘要翻译： 在N型阱中形成具有P +源极和P +漏极区域以及在其间延伸的沟道的P沟道单晶非易失性存储单元。 上覆的多晶硅浮栅通过薄氧化层与N阱分离。 P型扩散区形成在浮置栅极下面的N阱的一部分中，从而电容耦合到浮置栅极。 在该P型扩散区域内，形成用作电池的控制栅极的N型扩散区域。 P型扩散区域使控制栅极与N阱电隔离，使得可以将电压施加到控制栅极超过施加到N阱的电压，而不产生从控制栅极到N阱的电流路径 。 通过经由控制栅极将足够的电压耦合到浮置栅极同时偏置源极和漏极区域从而使电子从电池的P +漏极区域隧穿到浮动栅极来实现编程。 在一些实施例中，浮动栅极下方并由隧道氧化物层分离的附加P型扩散区用作存储单元的擦除栅。 在这样的实施例中，通过使电子从浮动栅极到擦除栅极隧穿来实现单元的擦除。

公开(公告)号：US07339229B2

公开(公告)日：2008-03-04

申请号：US11454916

申请日：2006-06-16

申请人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

发明人： Alex Wang ,  Shang-De Ted Chang ,  Han-Chih Lin ,  Tzeng-Huei Shiau ,  I-Sheng Liu ,  Hsien-Wen Liu

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/42328 ,  H01L29/7883

摘要： A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

摘要翻译： 用于多次编程应用的单多晶双晶体管PMOS存储器单元包括共享漏极/源极P +扩散区的PMOS浮栅晶体管，其中PMOS选择栅晶体管全部形成在第一n阱内。 用于浮栅晶体管的控制板形成在第二n阱中。 用于一次编程应用的单晶双转移器PMOS存储器单元包括具有在单个n阱中形成为p +扩散区的源的PMOS浮栅晶体管。 源极也适用于浮栅晶体管的控制板。

公开(公告)号：US5966329A

公开(公告)日：1999-10-12

申请号：US948147

申请日：1997-10-09

申请人： Ching-Hsiang Hsu ,  Shang-De Ted Chang ,  Nader Radjy

发明人： Ching-Hsiang Hsu ,  Shang-De Ted Chang ,  Nader Radjy

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10

摘要： A program voltage of a first level is applied to the control gate of a PMOS floating gate memory cell to realize an injection of hot electrons induced by band-to-band tunneling (BTBT) into the floating gate of the cell. As the threshold voltage of the cell increases due to the accumulation of charge on the floating gate, the injection of BTBT induced hot electrons subsides. The program voltage is reduced to a second level which induces the injection of channel hot electrons (CHE) into the floating gate, thereby boosting the rate of charge accumulation on the floating gate.

摘要翻译： 第一电平的编程电压被施加到PMOS浮栅存储器单元的控制栅极，以实现由频带隧穿（BTBT）引起的热电子注入到电池的浮动栅极中。 随着电池的阈值电压由于浮动栅极上的电荷的积累而增加，BTBT引起的热电子的注入减弱。 程序电压降低到第二电平，其引起通道热电子（CHE）注入到浮置栅极中，从而提高浮置栅极上的电荷积累速率。