公开(公告)号：US10705362B2

公开(公告)日：2020-07-07

申请号：US16023577

申请日：2018-06-29

Applicant: Shanghai Tianma Micro-electronics Co., Ltd.

Inventor： Cheng Fu ,  Yincheng Ding ,  Xiaosong Song ,  Chuanzhi Xu ,  Mengning Hu ,  Xiaoye Li

IPC: G02F1/1333 ,  F21V8/00 ,  G06F3/041 ,  H01L27/32 ,  H01L51/00 ,  H01L51/52

Abstract: A curved display device and a fabrication method are provided. The curved display device comprises: a cover lens; a display panel, wherein the display panel and the cover lens are bonded together as an integral having a curved surface; and a module, wherein a supporter is provided at each of at least two ends of the module. The supporter provided at the each of at least two ends of the module is directly bonded to the cover lens.

公开(公告)号：US10431601B2

公开(公告)日：2019-10-01

申请号：US16039334

申请日：2018-07-19

Applicant: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD. ,  TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Chuanzhi Xu ,  Zhengfang Xie ,  Xiongping Li ,  Xiaoyang Tong

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1368 ,  H01L21/441 ,  H01L21/467 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1362

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

公开(公告)号：US20180366495A1

公开(公告)日：2018-12-20

申请号：US16112792

申请日：2018-08-27

Applicant: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Chuanzhi Xu ,  Zhengfang Xie

IPC: H01L27/12

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/122 ,  G02F2201/56 ,  G06F3/044 ,  H01L27/1218

Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a display region and a border region. The border region includes a first border and a second border arranged oppositely in a first direction. The display region includes a hollowed-out region, a second sub-display region and a primary display region, a data drive port located in the border region and data lines extended in the first direction. The data lines include second data lines located in the second sub-display region and auxiliary data lines located in the primary display region. The data drive port provides a data signal to sub-pixels in the second sub-display region through the auxiliary data lines and the second data lines.

公开(公告)号：US20180323221A1

公开(公告)日：2018-11-08

申请号：US16039334

申请日：2018-07-19

Applicant: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD. ,  TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Chuanzhi Xu ,  Zhengfang Xie ,  Xiongping Li ,  Xiaoyang Tong

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/24 ,  G02F1/1343 ,  H01L21/441 ,  H01L21/467 ,  G02F1/1368 ,  G02F1/1362

CPC classification number: H01L27/1225 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2201/122 ,  H01L21/441 ,  H01L21/467 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

公开(公告)号：US10056410B2

公开(公告)日：2018-08-21

申请号：US15403131

申请日：2017-01-10

Applicant: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD. ,  TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Chuanzhi Xu ,  Zhengfang Xie ,  Xiongping Li ,  Xiaoyang Tong

IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/441 ,  H01L21/467 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1362

CPC classification number: H01L27/1225 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2201/122 ,  H01L21/441 ,  H01L21/467 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

公开(公告)号：US20170148825A1

公开(公告)日：2017-05-25

申请号：US15403131

申请日：2017-01-10

Applicant: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD. ,  TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Chuanzhi Xu ,  Zhengfang Xie ,  Xiongping Li ,  Xiaoyang Tong

IPC: H01L27/12 ,  H01L21/441 ,  H01L29/423 ,  G02F1/1368 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1343 ,  H01L21/467 ,  H01L29/24

CPC classification number: H01L27/1225 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2201/122 ,  H01L21/441 ,  H01L21/467 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method for manufacturing an array substrate, and an array substrate, a display panel and a display device are provided. The method may include: forming, on one side of a substrate, a gate electrode layer, a gate insulation layer and a semiconductor layer, wherein the gate electrode layer has a same pattern as the semiconductor layer; forming an etching stop layer on the semiconductor layer; forming a first, second hole and third through holes by patterning the etching stop layer; forming a source electrode layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; forming an active layer by etching the semiconductor layer at the location corresponding to the third through hole.

公开(公告)号：US10586813B2

公开(公告)日：2020-03-10

申请号：US16112792

申请日：2018-08-27

Applicant: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.

Inventor： Chuanzhi Xu ,  Zhengfang Xie

IPC: H01L27/12 ,  G06F3/044 ,  G02F1/1362 ,  G02F1/1368

Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a display region and a border region. The border region includes a first border and a second border arranged oppositely in a first direction. The display region includes a hollowed-out region, a second sub-display region and a primary display region, a data drive port located in the border region and data lines extended in the first direction. The data lines include second data lines located in the second sub-display region and auxiliary data lines located in the primary display region. The data drive port provides a data signal to sub-pixels in the second sub-display region through the auxiliary data lines and the second data lines.