公开(公告)号：US20070250721A1

公开(公告)日：2007-10-25

申请号：US11408226

申请日：2006-04-20

申请人： Shawn Searles ,  Scott Johnson ,  Grace Chuang

发明人： Shawn Searles ,  Scott Johnson ,  Grace Chuang

IPC分类号： G06F1/00

CPC分类号： G06F1/28

摘要： A method and apparatus for powering up an integrated circuit (IC). An IC includes a plurality of power domains each coupled to receive power from one of a plurality of power sources. Each power domain includes a power-sensing unit. A power-sensing unit in a first one of the plurality of power domains is coupled to receive a first power ok signal from an upstream power domain, and is configured to assert a second power ok signal to be provided to a second power domain. A power-sensing unit in the second power domain is coupled to detect the presence of voltage in the first power domain, and to receive the first power ok signal. When the power-sensing unit in the second power domain has both sensed the presence of power in the first power domain and received the second power ok signal, a third power ok signal is asserted.

摘要翻译： 一种用于为集成电路（IC）供电的方法和装置。 IC包括多个功率域，每个功率域被耦合以从多个电源之一接收功率。 每个功率域包括功率感测单元。 多个功率域中的第一个功率区中的功率感测单元被耦合以从上游功率域接收第一功率ok信号，并且被配置为断言要提供给第二功率域的第二功率ok信号。 耦合第二功率域中的功率感测单元以检测第一功率域中的电压的存在并接收第一功率ok信号。 当第二功率域中的功率感测单元已经感测到在第一功率域中存在功率并且接收到第二功率ok信号时，断言第三功率确认信号。

公开(公告)号：US07983362B2

公开(公告)日：2011-07-19

申请号：US12100996

申请日：2008-04-10

申请人： Shawn Searles ,  Grace Chuang ,  Christopher M. Kurker ,  Curtis M. Brody

发明人： Shawn Searles ,  Grace Chuang ,  Christopher M. Kurker ,  Curtis M. Brody

IPC分类号： H04L27/00

CPC分类号： H03K3/356139 ,  G11C7/1066 ,  G11C7/22

摘要： Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output signal. The linear receiver compares the DQ signal to the reference voltage, and generates the differential output signal in response to the comparison. A sense amplifier is coupled to the linear receiver. The sense amplifier has input nodes connected to the output nodes of the linear receiver, and an output node for a binary output signal having voltage characteristics compatible with the processor. The sense amplifier transforms the differential output signal into the binary output signal. The receiver architecture also includes a programming architecture coupled to the linear receiver to set operating characteristics of the linear receiver.

摘要翻译： 提供了数据处理器的接收机架构和偏置电路。 接收器架构包括具有用于数据（DQ）信号的第一输入节点，用于参考电压的第二输入节点和用于差分输出信号的输出节点的线性接收器。 线性接收器将DQ信号与参考电压进行比较，并响应于比较而产生差分输出信号。 读出放大器耦合到线性接收器。 读出放大器具有连接到线性接收器的输出节点的输入节点和具有与处理器兼容的电压特性的二进制输出信号的输出节点。 读出放大器将差分输出信号转换为二进制输出信号。 接收机架构还包括耦合到线性接收机的编程架构以设置线性接收机的操作特性。

公开(公告)号：US07826279B2

公开(公告)日：2010-11-02

申请号：US12100999

申请日：2008-04-10

申请人： Shawn Searles ,  Grace Chuang ,  Christopher M. Kurker ,  Curtis M. Brody

发明人： Shawn Searles ,  Grace Chuang ,  Christopher M. Kurker ,  Curtis M. Brody

IPC分类号： G11C7/00

CPC分类号： G06F13/4243

摘要： Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage.

摘要翻译： 提供了数据处理器的接收机架构和相关偏置电路。 用于计算机处理器的接收器架构的一个实施例包括被配置为接收第一输入，第二输入和第一偏置电压的第一线性接收器级。 第一线性接收机级被配置为响应于第一输入和第二输入之间的比较而产生第一差分输出信号。 第一差分输出信号具有受第一偏置电压影响的指定可编程电压摆幅。 接收机架构还包括耦合到第一线性接收机级的第一可编程偏置电路。 第一可编程偏置电路被配置为产生第一偏置电压。

公开(公告)号：US07652937B2

公开(公告)日：2010-01-26

申请号：US12100979

申请日：2008-04-10

申请人： Shawn Searles ,  Grace Chuang ,  Christopher M. Kurker ,  Curtis M. Brody

发明人： Shawn Searles ,  Grace Chuang ,  Christopher M. Kurker ,  Curtis M. Brody

IPC分类号： G11C7/00

CPC分类号： G06F13/4243 ,  G11C7/10

摘要： Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture includes three linear receiver stages coupled in series. The first stage receives a differential data strobe (DQS) input signal associated with a plurality of data (DQ) signals, and the first stage has a first programmable swing voltage associated therewith. The second stage has a programmable shift voltage associated therewith, and the third stage has a second programmable swing voltage associated therewith. The receiver architecture also includes a programming architecture coupled to the first stage, the second stage, and the third stage. The programming architecture is configured to set the first programmable swing voltage, the programmable shift voltage, and the second programmable swing voltage.

摘要翻译： 提供了数据处理器的接收机架构和相关偏置电路。 接收机架构的一个实施例包括串联耦合的三个线性接收机级。 第一级接收与多个数据（DQ）信号相关联的差分数据选通（DQS）输入信号，并且第一级具有与其相关联的第一可编程摆幅电压。 第二级具有与其相关联的可编程移位电压，并且第三级具有与其相关联的第二可编程摆幅电压。 接收器架构还包括耦合到第一阶段，第二阶段和第三阶段的编程架构。 编程架构被配置为设置第一可编程摆幅电压，可编程移位电压和第二可编程摆幅电压。

公开(公告)号：US20120159271A1

公开(公告)日：2012-06-21

申请号：US12972977

申请日：2010-12-20

申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

IPC分类号： G06F11/263

CPC分类号： G11C29/1201 ,  G11C29/022

摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

公开(公告)号：US07961533B2

公开(公告)日：2011-06-14

申请号：US12127059

申请日：2008-05-27

申请人： Shawn Searles

发明人： Shawn Searles

IPC分类号： G11C7/00

CPC分类号： G06F13/1689

摘要： Methods and apparatus for aligning a clock signal and a set of strobe signals are disclosed. In one embodiment, a memory controller includes a clock generator configured to generate the clock signal, and a respective strobe signal generator configured to generate each strobe signal. The memory controller further includes a phase recovery engine configured to receive an error signal from a corresponding memory device, wherein the error signal conveys an error indication indicative of an alignment of the strobe signal relative to the clock signal for each of a plurality of cycles of the strobe signal. The phase recovery engine includes an accumulator configured to maintain an accumulation value that depends upon the error indications for the plurality of cycles of the strobe signal. The strobe signal generator is configured to control a delay associated with generation of the strobe signal depending upon the accumulation value.

摘要翻译： 公开了用于对准时钟信号和一组选通信号的方法和装置。 在一个实施例中，存储器控制器包括被配置为产生时钟信号的时钟发生器和被配置为产生每个选通信号的相应选通信号发生器。 存储器控制器还包括相位恢复引擎，其被配置为从相应的存储器件接收错误信号，其中，误差信号传送指示针对多个周期中的每个周期的选通信号相对于时钟信号的对准的错误指示 选通信号。 相位恢复引擎包括一个累加器，被配置为保持取决于选通信号的多个周期的错误指示的累加值。 选通信号发生器被配置为根据积累值来控制与产生选通信号相关联的延迟。

公开(公告)号：US07765425B1

公开(公告)日：2010-07-27

申请号：US11385329

申请日：2006-03-21

申请人： Shawn Searles ,  Donald Walters ,  Ravinder Rachala ,  Scott C. Johnson

发明人： Shawn Searles ,  Donald Walters ,  Ravinder Rachala ,  Scott C. Johnson

IPC分类号： G06F1/04

CPC分类号： G06F1/10

摘要： A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for clock skew detected between two clock signals by configuring variable delay adjusters located inline with the respective clock signals. Such a delay controller may also use the variable delay adjusters to correct duty cycle errors in a clock signal and may further utilize the variable delay adjusters to measure and characterize jitter detected on the clock signals.

摘要翻译： 一种用于使用位于集成电路上的各个点的可变延迟调节器来测量集成电路的时钟信号的时钟偏移和抖动的系统和方法。 集成电路的延迟控制器可以通过配置与各个时钟信号在一起的可变延迟调节器来测量和补偿在两个时钟信号之间检测到的时钟偏差。 这样的延迟控制器还可以使用可变延迟调整器来校正时钟信号中的占空比误差，并且还可以利用可变延迟调节器来测量和表征在时钟信号上检测到的抖动。

公开(公告)号：US07701263B2

公开(公告)日：2010-04-20

申请号：US12059595

申请日：2008-03-31

申请人： Anil Kumar ,  Shawn Searles

发明人： Anil Kumar ,  Shawn Searles

IPC分类号： H03B1/00

CPC分类号： H03K19/00315 ,  H03K17/102

摘要： An apparatus including a bias voltage generator and one or more cascode drivers. Each of the one or more cascode drivers may include a plurality of cascode transistors. The bias voltage generator may control the cascode bias voltages provided to the cascode transistors based on a plurality of programmable control bits received by the bias voltage generator. The received plurality of programmable control bits may include a first set of programmable control bits, which may be used to control the magnitude of the cascode bias voltages, and a second set of programmable control bits, which may be used to control the stability of the cascode bias voltages.

摘要翻译： 一种包括偏置电压发生器和一个或多个共源共栅驱动器的装置。 一个或多个共源共栅驱动器中的每一个可以包括多个共源共栅晶体管。 偏置电压发生器可以基于由偏置电压发生器接收的多个可编程控制位来控制提供给共源共栅晶体管的共源共栅偏置电压。 所接收的多个可编程控制位可以包括第一组可编程控制位，其可用于控制共源共栅偏置电压的幅度，以及第二组可编程控制位，其可用于控制 共源共栅偏置电压。

公开(公告)号：US07652524B2

公开(公告)日：2010-01-26

申请号：US12018297

申请日：2008-01-23

申请人： Dimitry Patent ,  Ravinder Rachala ,  Shawn Searles ,  Lena Ahlen ,  Matthew Cooke

发明人： Dimitry Patent ,  Ravinder Rachala ,  Shawn Searles ,  Lena Ahlen ,  Matthew Cooke

IPC分类号： G05F1/10 ,  G05F3/02

CPC分类号： G05F3/262

摘要： An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node.

摘要翻译： 电子电路。 电子电路包括耦合到第一电源电压节点和第二电源电压节点的第一电路支路。 第一电路支路包括被配置为产生第一参考电流的第一参考电流电路和被配置为产生第二参考电流的第二参考电流电路。 电子电路还包括与第一电路支路并联耦合的第二电路支路。 第二电路支路包括耦合以与第一参考电流电路形成电流镜的第一晶体管，以及耦合以与第二参考电流电路形成电流镜的第二晶体管。 第一和第二晶体管中的每一个的源极端子耦合在一起以形成第三电源电压节点。

公开(公告)号：US20090184696A1

公开(公告)日：2009-07-23

申请号：US12018297

申请日：2008-01-23

申请人： Dimitry Patent ,  Ravinder Rachala ,  Shawn Searles ,  Lena Ahlen ,  Matthew Cooke

发明人： Dimitry Patent ,  Ravinder Rachala ,  Shawn Searles ,  Lena Ahlen ,  Matthew Cooke

IPC分类号： G05F1/10

CPC分类号： G05F3/262

摘要： An electronic circuit. The electronic circuit includes a first circuit leg coupled to a first supply voltage node and a second supply voltage node. The first circuit leg includes a first reference current circuit configured to produce a first reference current and a second reference current circuit configured to produce a second reference current. The electronic circuit further includes a second circuit leg coupled in parallel with the first circuit leg. The second circuit leg includes a first transistor coupled to form a current mirror with the first reference current circuit and a second transistor coupled to form a current mirror with the second reference current circuit. The source terminals of each of the first and second transistors are coupled together to form a third supply voltage node

摘要翻译： 电子电路。 电子电路包括耦合到第一电源电压节点和第二电源电压节点的第一电路支路。 第一电路支路包括被配置为产生第一参考电流的第一参考电流电路和被配置为产生第二参考电流的第二参考电流电路。 电子电路还包括与第一电路支路并联耦合的第二电路支路。 第二电路支路包括耦合以与第一参考电流电路形成电流镜的第一晶体管，以及耦合以与第二参考电流电路形成电流镜的第二晶体管。 第一和第二晶体管中的每一个的源极端子耦合在一起以形成第三电源电压节点