公开(公告)号：US5538907A

公开(公告)日：1996-07-23

申请号：US241358

申请日：1994-05-11

申请人： Sheldon Aronowitz ,  Rosario Consiglio ,  Abraham Yee

发明人： Sheldon Aronowitz ,  Rosario Consiglio ,  Abraham Yee

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L27/07 ,  H01L27/092 ,  H01L21/265

CPC分类号： H01L27/0255 ,  H01L27/0251 ,  H01L27/0259 ,  H01L27/0623 ,  H01L27/0629 ,  H01L27/0716 ,  H01L27/092

摘要： A CMOS integrate circuit has improved protection to damage from electrostatic discharge (ESD) events because the circuit is formed with a virtual lateral bipolar transistor submerged in the morphology of the integrated circuit beneath an active circuit element of the circuit, and being formed by impurity atoms implanted into the substrate structure as ions which disperse laterally to form a dispersed charge permeation zone through which surge current from an ESD is conducted safely at a current level sufficiently low that the substrate material of the integrated circuit is not damaged. The integrated circuit may be formed with an intrinsic zener diode having a reverse bias breakdown voltage high enough to not interfere with the normal operation of the integrated circuit, and low enough to allow surge current from an ESD event to safely flow to ground potential.

摘要翻译： CMOS集成电路已经改善了对静电放电（ESD）事件的损害的保护，因为电路形成有浸没在电路的有源电路元件下面的集成电路形态的虚拟横向双极晶体管，并由杂质原子 以横向分散形成分散的电荷渗透区域的离子注入到衬底结构中，通过该区域，来自ESD的浪涌电流以足够低的电流水平安全地传导，使得集成电路的衬底材料不被损坏。 该集成电路可以由具有足够高的反偏压击穿电压的本征齐纳二极管形成，以不干扰集成电路的正常工作，并且足够低以允许来自ESD事件的浪涌电流安全地流向地电势。

公开(公告)号：US5815360A

公开(公告)日：1998-09-29

申请号：US761443

申请日：1996-12-06

申请人： Rosario Consiglio ,  Gina M. Sparacino

发明人： Rosario Consiglio ,  Gina M. Sparacino

IPC分类号： H01L27/02 ,  H02H9/04 ,  H03K19/003 ,  H02H1/00

CPC分类号： H03K19/00315 ,  H01L27/0251 ,  H02H9/046

摘要： An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

摘要翻译： 具有输入/输出门电压调节和寄生齐纳和结二极管的集成电路结构，用于防止由静电放电（ESD）事件引起的损坏。 电路包括连接在集成电路的输入/输出焊盘和接地电位之间的第一保护FET。 二极管稳压器也连接在第一保护FET的栅极和集成电路的参考电位之间。 第一保护FET在ESD事件期间从其栅 - 漏重叠电容接收电压。 二极管在ESD事件期间操作以向第一FET栅极提供足够的电压，以允许期望的ESD电流流过第一保护FET。 在一个实施例中，第一FET是NMOS器件，二极管电压调节器是一系列p-n正向偏置二极管。

公开(公告)号：US5594611A

公开(公告)日：1997-01-14

申请号：US180741

申请日：1994-01-12

申请人： Rosario Consiglio ,  Gina M. Sparacino

发明人： Rosario Consiglio ,  Gina M. Sparacino

IPC分类号： H01L27/02 ,  H02H9/04 ,  H03K19/003 ,  H02H9/00

CPC分类号： H03K19/00315 ,  H01L27/0251 ,  H02H9/046

摘要： An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

摘要翻译： 具有输入/输出门电压调节和寄生齐纳和结二极管的集成电路结构，用于防止由静电放电（ESD）事件引起的损坏。 电路包括连接在集成电路的输入/输出焊盘和接地电位之间的第一保护FET。 二极管稳压器也连接在第一保护FET的栅极和集成电路的参考电位之间。 第一保护FET在ESD事件期间从其栅 - 漏重叠电容接收电压。 二极管在ESD事件期间操作以向第一FET栅极提供足够的电压，以允许期望的ESD电流流过第一保护FET。 在一个实施例中，第一FET是NMOS器件，二极管电压调节器是一系列p-n正向偏置二极管。

公开(公告)号：US5707886A

公开(公告)日：1998-01-13

申请号：US712896

申请日：1996-09-12

申请人： Rosario Consiglio ,  Gina M. Sparacino

发明人： Rosario Consiglio ,  Gina M. Sparacino

IPC分类号： H01L27/02 ,  H02H9/04 ,  H03K19/003 ,  H01L21/70

CPC分类号： H03K19/00315 ,  H01L27/0251 ,  H02H9/046

摘要： An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

摘要翻译： 具有输入/输出门电压调节和寄生齐纳和结二极管的集成电路结构，用于防止由静电放电（ESD）事件引起的损坏。 电路包括连接在集成电路的输入/输出焊盘和接地电位之间的第一保护FET。 二极管稳压器也连接在第一保护FET的栅极和集成电路的参考电位之间。 第一保护FET在ESD事件期间从其栅 - 漏重叠电容接收电压。 二极管在ESD事件期间操作以向第一FET栅极提供足够的电压，以允许期望的ESD电流流过第一保护FET。 在一个实施例中，第一FET是NMOS器件，二极管电压调节器是一系列p-n正向偏置二极管。

公开(公告)号：US5682047A

公开(公告)日：1997-10-28

申请号：US484003

申请日：1995-06-07

申请人： Rosario Consiglio ,  Yen-Hui Ku

发明人： Rosario Consiglio ,  Yen-Hui Ku

IPC分类号： H01L27/02 ,  H01L23/63 ,  H01L29/76 ,  H02H3/22 ,  H02H9/00

CPC分类号： H01L27/0262 ,  H01L27/0251

摘要： An input/output structure includes a microelectronic device connected in circuit between a contact pad and a reference potential, and a thyristor device for protecting the microelectronic device from electrostatic discharge. The thyristor device includes first and second terminals connected to the contact pad and to the reference potential respectively, a PNPN thyristor structure including a first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage. A differentiator including a capacitor connected between the first terminal and the electrode and a resistor connected between the second terminal and the electrode prevents false triggering during normal operation. A metal interconnection layer includes an anode section which is connected to the N-region and to the second terminal, and a cathode section which is connected to the P-region, the first terminal and the electrode, such that the cathode section laterally surrounds the anode section.

摘要翻译： 输入/输出结构包括连接在接触焊盘和参考电位之间的电路中的微电子器件，以及用于保护微电子器件免受静电放电的晶闸管器件。 晶闸管器件包括分别连接到接触焊盘和参考电位的第一和第二端子，PNPN晶闸管结构包括第一P区，第一N区，第二P区和第二N区， 串联在第一和第二端子之间，以及用于将电场引入第二P区域的电极。 感应电场增加了第二P区中的电荷载流子的数量，并且使得能够以施加在第一和第二端子之间的较低电压来触发装置。 电极包括绝缘栅极，并且可以连接到第一端子或第二端子。 栅极可以包括厚场氧化物层或薄氧化物层，以进一步降低触发电压。 包括连接在第一端子和电极之间的电容器的微分器和连接在第二端子和电极之间的电阻器防止正常操作期间的错误触发。 金属互连层包括连接到N区和第二端的阳极部分和连接到P区域，第一端子和电极的阴极部分，使得阴极部分横向围绕 阳极部分。

公开(公告)号：US5637887A

公开(公告)日：1997-06-10

申请号：US475586

申请日：1995-06-07

申请人： Rosario Consiglio

发明人： Rosario Consiglio

IPC分类号： H01L27/02 ,  H01L29/74 ,  H01L29/749 ,  H01L29/87 ,  H02H3/00 ,  H02H7/00

CPC分类号： H01L27/0262 ,  H01L27/0266 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87

摘要： A thyristor device includes first and second terminals, a PNPN thyristor structure including first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage. A differentiator including a capacitor connected between the first terminal and the electrode and a resistor connected between the second terminal and the electrode prevents false triggering during normal operation. A metal interconnection layer includes an anode section which is connected to the N-region and to the second terminal, and a cathode section which is connected to the P-region, the first terminal and the electrode, such that the cathode section laterally surrounds the anode section.

摘要翻译： 晶闸管器件包括第一和第二端子，PNPN晶闸管结构包括第一P区，第一N区，第二P区和第二N区，串联布置在第一和第二端子之间， 在第二P区域中产生电场。 感应电场增加了第二P区中的电荷载流子的数量，并且使得能够以施加在第一和第二端子之间的较低电压来触发装置。 电极包括绝缘栅极，并且可以连接到第一端子或第二端子。 栅极可以包括厚场氧化物层或薄氧化物层，以进一步降低触发电压。 包括连接在第一端子和电极之间的电容器的微分器和连接在第二端子和电极之间的电阻器防止正常操作期间的错误触发。 金属互连层包括连接到N区和第二端的阳极部分和连接到P区域，第一端子和电极的阴极部分，使得阴极部分横向围绕 阳极部分。