公开(公告)号：US08316440B1

公开(公告)日：2012-11-20

申请号：US11929305

申请日：2007-10-30

申请人： Sheng-Chi Hsieh ,  Chao-Yu Chen ,  Chih-Chia Chen

发明人： Sheng-Chi Hsieh ,  Chao-Yu Chen ,  Chih-Chia Chen

IPC分类号： G06F11/00 ,  G06F12/14 ,  G06F12/16 ,  G08B23/00

CPC分类号： G06F11/108 ,  G06F11/302 ,  G06F11/3051 ,  H04L63/1416 ,  H04L63/1425 ,  H04L63/1483

摘要： Detection for pharming attacks and specifically for changes in name-to-IP resolutions on a computer system using rules is described. The DNS settings and the Hosts file on a computer system are monitored and their modification information is saved as a part of the historical data over time. When an IP address is determined for a host name, various rules are applied to the IP address in connection with the saved historical data, such that each rule produces a score based on various criteria. Different rules may have different weights assigned to their scores. The scores of all the rules are summed up to produce a final score. If the final score is above a predefined value, then there is a suspicious change in the IP address, and an alert is sent. Otherwise, the host name and the IP address are saved as a part of the historical data.

摘要翻译： 描述了使用规则检测计算机系统上的制毒攻击，特别是在名称到IP分辨率上的更改。 监视计算机系统上的DNS设置和主机文件，并将其修改信息作为历史数据的一部分保存。 当为主机名确定IP地址时，将与保存的历史数据相关联的IP地址应用各种规则，使得每个规则基于各种标准产生分数。 不同的规则可能具有不同的权重分配给他们的分数。 所有规则的得分总结出来，以产生最终得分。 如果最终得分高于预定值，则IP地址中存在可疑的更改，并发送警报。 否则，主机名和IP地址将作为历史数据的一部分进行保存。

公开(公告)号：US08922230B2

公开(公告)日：2014-12-30

申请号：US13105603

申请日：2011-05-11

申请人： Mill-Jer Wang ,  Chih-Chia Chen ,  Hung-Chih Lin ,  Ching-Nen Peng ,  Hao Chen

发明人： Mill-Jer Wang ,  Chih-Chia Chen ,  Hung-Chih Lin ,  Ching-Nen Peng ,  Hao Chen

IPC分类号： G01R31/20 ,  G01R1/073

CPC分类号： G01R31/2884 ,  G01R1/07378 ,  G01R31/2834 ,  G01R31/2886 ,  H01L22/14 ,  Y02P80/30

摘要： A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.

摘要翻译： 三维（3D）集成电路（IC）测试装置包括多个连接装置。 当由测试模式操作诸如由多个3D裸片形成的插入器或3D IC的受测设备（DUT）时，3D IC测试装置经由诸如探针的各种接口通道耦合到DUT。 DUT中的连接装置和各种通孔通孔（TSV）形成一个TSV链，以便可以一次性地测试各种TSV的电特性测试。

公开(公告)号：US20120286814A1

公开(公告)日：2012-11-15

申请号：US13105603

申请日：2011-05-11

申请人： Mill-Jer Wang ,  Chih-Chia Chen ,  Hung-Chih Lin ,  Ching-Nen Peng ,  Hao Chen

发明人： Mill-Jer Wang ,  Chih-Chia Chen ,  Hung-Chih Lin ,  Ching-Nen Peng ,  Hao Chen

IPC分类号： G01R31/20 ,  H01L21/66

CPC分类号： G01R31/2884 ,  G01R1/07378 ,  G01R31/2834 ,  G01R31/2886 ,  H01L22/14 ,  Y02P80/30

摘要： A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once.

摘要翻译： 三维（3D）集成电路（IC）测试装置包括多个连接装置。 当由测试模式操作诸如由多个3D裸片形成的插入器或3D IC的受测设备（DUT）时，3D IC测试装置经由诸如探针的各种接口通道耦合到DUT。 DUT中的连接装置和各种通孔通孔（TSV）形成一个TSV链，以便可以一次性地测试各种TSV的电特性测试。

公开(公告)号：US07920222B2

公开(公告)日：2011-04-05

申请号：US12044029

申请日：2008-03-07

申请人： Chih-Chia Chen ,  Chien-Yuan Chen

发明人： Chih-Chia Chen ,  Chien-Yuan Chen

IPC分类号： G02F1/1333 ,  H02B1/01 ,  G09F13/04

CPC分类号： G02F1/133308 ,  G02F2001/133314 ,  G02F2001/133317 ,  G02F2201/503

摘要： A liquid crystal display (LCD) includes a backlight module, a cell module installed in front of the backlight module, and a front frame which includes a frame body with holes and buffer material. The buffer material has a first part disposed in the holes and fixed to the cell module and backlight module through the front frame, and a second part sandwiched between the frame body and cell module. A method for manufacturing a LCD device is also provided, including forming a buffer material on a frame body by injection molding, firmly connecting the frame body, a cell module, and a backlight module, and locating the buffer material between the frame body and cell module.

摘要翻译： 液晶显示器（LCD）包括背光模块，安装在背光模块前面的单元模块和包括具有孔和缓冲材料的框体的前框架。 缓冲材料具有设置在孔中的第一部分，并且通过前框架固定到电池模块和背光模块，以及夹在框体和电池模块之间的第二部分。 还提供了一种用于制造LCD装置的方法，包括通过注射成型在框体上形成缓冲材料，牢固地连接框体，电池模块和背光模块，并将缓冲材料定位在框体与电池之间 模块。

公开(公告)号：US20100283396A1

公开(公告)日：2010-11-11

申请号：US12719844

申请日：2010-03-08

申请人： Chih-Chia Chen ,  Yung-Chun Chuang

发明人： Chih-Chia Chen ,  Yung-Chun Chuang

IPC分类号： H05B37/02

CPC分类号： H05B33/0812 ,  H05B33/0827 ,  H05B33/0845 ,  Y02B20/345

摘要： A light source driving circuit includes a plurality of light-emitting loads, an operational amplifier, a plurality of transistors, an isolation circuit, and a reference circuit. The first ends of each transistor are electrically connected to the plurality of light-emitting loads respectively. The second end of each transistor is electrically connected to a current mirror. The control end of each transistor is electrically connected to the output end of the operational amplifier. The isolation circuit is electrically connected between the negative input end of the operational amplifier and the plurality of transistors.

摘要翻译： 光源驱动电路包括多个发光负载，运算放大器，多个晶体管，隔离电路和参考电路。 每个晶体管的第一端分别电连接到多个发光负载。 每个晶体管的第二端电连接到电流镜。 每个晶体管的控制端电连接到运算放大器的输出端。 隔离电路电连接在运算放大器的负输入端和多个晶体管之间。

公开(公告)号：US09557354B2

公开(公告)日：2017-01-31

申请号：US13362576

申请日：2012-01-31

申请人： Chih-Chia Chen ,  Kuan-Yu Lin ,  Chin-Chou Liu

发明人： Chih-Chia Chen ,  Kuan-Yu Lin ,  Chin-Chou Liu

IPC分类号： G01R19/165 ,  H03K5/24 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R19/16552 ,  G01R31/2856 ,  G01R31/318513 ,  H03K5/24

摘要： A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal.

摘要翻译： 包括接收输入参考电压的第一开关，接收输入测试电压的第二开关，第一开关和第二开关的电路并联电连接。 电路还包括与第一开关和第二开关串联电连接的第一电容器。 电路还包括反馈级，其包括与反馈开关并联电连接的反馈反相器，其中反馈级与第一电容器串联电连接。 电路还包括与反馈级串联电连接的第一反相器和与第一反相器串联电连接的第三开关。 电路还包括与第三反相器并联电连接的第二反相器，第二反相器和第三反相器与第三开关串联电连接，并且第三反相器输出第一输出信号。

公开(公告)号：US20100060339A1

公开(公告)日：2010-03-11

申请号：US12252369

申请日：2008-10-16

申请人： Chih-Chia Chen ,  Chien-Chuan Chung

发明人： Chih-Chia Chen ,  Chien-Chuan Chung

IPC分类号： H03L5/00

CPC分类号： H03K19/018521

摘要： A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage.

摘要翻译： 公开了一种具有升压机构的电压电平移位器，用于连接具有不同工作电压摆幅的两个电路单元。 电压电平移位器包括第一反相器，第二反相器，第一电容器，第二电容器和多个晶体管。 第一反相器的输入端和电源端分别接收输入电压和第一电压。 第二反相器的输出端用于提供输出电压。 当输入电压为接地电压时，输出电压也为接地电压; 同时，控制开关以将第一和第二电容器分别充电到第二电压和第三电压。 当输入电压为第一电压时，将第一，第二和第三电压的和电压提供给第二逆变器的功率端，以提供和电压作为输出电压。

公开(公告)号：US20070227671A1

公开(公告)日：2007-10-04

申请号：US11758280

申请日：2007-06-05

申请人： Chih-Chia Chen

发明人： Chih-Chia Chen

IPC分类号： B65C9/26

CPC分类号： G02F1/13452 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/10674 ,  Y10T156/17 ,  Y10T156/1744 ,  Y10T428/2839

摘要： An adhesive structure for use in a liquid crystal display (LCD) and a method for manufacturing the adhesive structure are provided. The adhesive structure includes a releasing paper which is provided with two anisotropic conductive films (ACFs) thereon. When the adhesive structure is attached onto the LCD, the two ACFs can be simultaneously attached onto the glass substrate of the LCD for connecting the integrated circuit and flexible printed circuit, respectively.

摘要翻译： 提供了一种用于液晶显示器（LCD）的粘合剂结构及其制造方法。 粘合剂结构包括在其上设置有两个各向异性导电膜（ACF）的脱模纸。 当粘合剂结构附着到LCD上时，两个ACF可以同时附着在LCD的玻璃基板上，用于分别连接集成电路和柔性印刷电路。

公开(公告)号：US08350603B2

公开(公告)日：2013-01-08

申请号：US13005006

申请日：2011-01-12

申请人： Chih-Chia Chen

发明人： Chih-Chia Chen

IPC分类号： H03K3/00

CPC分类号： H03K19/0016 ,  H03K19/00

摘要： A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised.

摘要翻译： 电路包括逆变器。 逆变器反相具有输入低电压电平和输入高电压电平的输入信号，以形成具有输出高电压电平和输出低电压电平的输出信号。 与输入高电平相比，输出高电平降低。 或者或另外，与输入低电压电平相比，输出低电压电平升高。

公开(公告)号：US20130007692A1

公开(公告)日：2013-01-03

申请号：US13172248

申请日：2011-06-29

申请人： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

发明人： Chao-Yang Yeh ,  Ze-Ming Wu ,  Meng-Lin Chung ,  Chih-Chia Chen ,  Li-Fu Ding ,  Sa-Lly Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium.

摘要翻译： 一种方法包括使用机器实施的RC提取工具来分析半导体插入器上的前侧导电图案和背面导电图案，并将表示多个相应RC节点的数据从RC提取工具输出到有形的持久机器可读存储介质。 产生半导体插入器的衬底网格模型，其具有多个衬底网格节点。 每个衬底网格节点通过相应的衬底阻抗元件连接到多个衬底网格节点中的相邻衬底网格节点。 形成了一组时序分析工具的输入。 多个RC节点连接到衬底网格模型的多个衬底网格节点中的一个。 该组输入存储在有形机器可读存储介质中。