公开(公告)号：US20130093091A1

公开(公告)日：2013-04-18

申请号：US13806136

申请日：2011-08-05

申请人： Shenglin Ma ,  Yunhui Zhu ,  Xin Sun ,  Yufeng Jin ,  Min Miao

发明人： Shenglin Ma ,  Yunhui Zhu ,  Xin Sun ,  Yufeng Jin ,  Min Miao

IPC分类号： H01L23/522 ,  H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/50 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield.

摘要翻译： 本发明公开了一种三维垂直互连结构及其制造方法。 该结构包括至少两层芯片，其顺序层叠或面对面堆叠，并且粘合材料用于在所述芯片的相邻层之间的粘合，每层芯片包含基底层和介电层顺序地底部 到达顶点; 芯片的前表面具有环形横截面的第一凹部，并且第一凹部内部填充有金属，以形成通过再分配层连接到芯片内的微电子器件的第一导电环; 具有与第一导电环的内环相同的半径和中心的第一贯穿层的切屑孔穿透堆叠的芯片，并且在其内部具有电连接到第一导电环的第一微导电极。 本发明的三维垂直互连结构增强了电互连的强度和相邻的芯片层之间的粘附力，同时所公开的制造方法简化了工艺难度，从而提高了产量。

公开(公告)号：US08836140B2

公开(公告)日：2014-09-16

申请号：US13806136

申请日：2011-08-05

申请人： Shenglin Ma ,  Min Miao ,  Yunhui Zhu ,  Xin Sun ,  Yufeng Jin

发明人： Shenglin Ma ,  Min Miao ,  Yunhui Zhu ,  Xin Sun ,  Yufeng Jin

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/50 ,  H01L25/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L21/50 ,  H01L21/76843 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2224/0557 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/83896 ,  H01L2224/9202 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06558 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring. The three-dimensional vertically interconnected structure of the present invention enhances the strength of the electric interconnection and the adhesion between adjacent layers of chips, and in the meantime the disclosed fabricating method simplifies the process difficulty and therefore improves the yield.

摘要翻译： 本发明公开了一种三维垂直互连结构及其制造方法。 该结构包括至少两层芯片，其顺序层叠或面对面堆叠，并且粘合材料用于在所述芯片的相邻层之间的粘合，每层芯片包含基底层和介电层顺序地底部 到达顶点; 芯片的前表面具有环形横截面的第一凹部，并且第一凹部内部填充有金属，以形成通过再分配层连接到芯片内的微电子器件的第一导电环; 具有与第一导电环的内环相同的半径和中心的第一贯穿层的切屑孔穿透堆叠的芯片，并且在其内部具有电连接到第一导电环的第一微导电极。 本发明的三维垂直互连结构增强了电互连的强度和相邻的芯片层之间的粘附力，同时所公开的制造方法简化了工艺难度，从而提高了产量。