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    Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change
    2.
    发明授权
    Voltage-boosting generator for reducing effects due to operating voltage variation and temperature change 有权
    电压升压发生器，用于减少由于工作电压变化和温度变化引起的影响

    公开(公告)号：US06580287B2

    公开(公告)日：2003-06-17

    申请号：US10099806

    申请日：2002-03-13

    申请人： Hsien-Wen Hsu ,  Yu-Shen Lin ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    发明人： Hsien-Wen Hsu ,  Yu-Shen Lin ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    IPC分类号： H03K19003

    CPC分类号： H02M3/07

    摘要： A voltage-boosting generator for reducing the effects due to operating voltage variation and temperature change. The generator comprises a delay line circuit and a voltage boosting circuit. The delay line circuit is used to perform a time delay according to an initial boosting signal and to produce a control signal. The voltage boosting circuit is used to boosted voltage according to the control signal.

    摘要翻译： 一种电压升压发生器，用于降低由于工作电压变化和温度变化引起的影响。 发电机包括延迟线电路和升压电路。 延迟线电路用于根据初始升压信号执行时间延迟并产生控制信号。 升压电路根据控制信号用于升压。

    NOR-structured semiconductor memory device
    3.
    发明授权
    NOR-structured semiconductor memory device 有权
    NOR结构的半导体存储器件

    公开(公告)号：US06563735B1

    公开(公告)日：2003-05-13

    申请号：US10117148

    申请日：2002-04-04

    申请人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    发明人： Hsin-Chien Chen ,  Gin-Liang Chen ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    IPC分类号： G11C1604

    CPC分类号： G11C16/0491

    摘要： A NOR-structured semiconductor memory device with a novel configuration of bit line connection is disclosed. The NOR-structured semiconductor memory device comprises a semiconductor memory cell array electrically connected to a plurality of bit lines. The plurality of bit lines are divided into at least four bit line groups. At least two bit lines of each bit line group are coupled to a main bit line through at least two bit line transistors, respectively. Furthermore, the bit lines of the NOR-structured semiconductor memory device are arranged in such a way that at least four adjacent bit lines thereof are selected from four different bit line groups and coupled to four different main bit lines, respectively. During a programming or data reading operation, two adjacent bit lines of the four adjacent bit lines are supplied with a programming voltage or sense current while the other two adjacent bit lines are grounded. Therefore, the NOR-structured semiconductor memory device successfully prevents the programming disturbance or correctly determines the data stored in memory cells at a high speed because no leakage current path is formed.

    摘要翻译： 公开了具有位线连接的新颖结构的NOR结构的半导体存储器件。 NOR结构的半导体存储器件包括电连接到多个位线的半导体存储单元阵列。 多个位线被分成至少四个位线组。 每个位线组的至少两个位线分别通过至少两个位线晶体管耦合到主位线。 此外，NOR结构半导体存储器件的位线被布置成使得其中至少四个相邻的位线分别从四个不同的位线组中选择并且分别耦合到四个不同的主位线。 在编程或数据读取操作期间，四个相邻位线中的两个相邻位线被提供有编程电压或感测电流，而另外两个相邻位线接地。 因此，由于没有形成泄漏电流路径，所以NOR结构的半导体存储器件成功地防止了编程干扰或者以高速正确地确定存储在存储单元中的数据。

    Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect
    4.
    发明授权
    Method for designing circuit layout of non-neighboring metal bit lines to reduce coupling effect 有权
    设计非相邻金属位线的电路布局以减少耦合效应的方法

    公开(公告)号：US06618848B2

    公开(公告)日：2003-09-09

    申请号：US09814409

    申请日：2001-03-22

    申请人： Han-Sung Chen ,  Kuo-Yu Liao ,  Yung-Feng Lin ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    发明人： Han-Sung Chen ,  Kuo-Yu Liao ,  Yung-Feng Lin ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    IPC分类号： G06F1750

    CPC分类号： G11C7/18 ,  G11C17/12

    摘要： A method for designing a circuit layout of non-neighboring metal bit lines to reduce coupling effect in sensing operation is disclosed. The method comprises providing a memory array having a plurality of bit lines arranged sequentially, wherein every two adjacent bit lines are paired in the sensing operation of a memory cell in the memory array. The first embodiment is presented by assigning a first pair of the bit lines permuted with each other to create a non-neighboring bit line layout. The second embodiment is presented by inserting one of a second pair of the bit lines into a first pair of bit lines to separate the first pair of bit lines in layout design. The method further comprises shrinking the layout space between two adjacent non-paired bit lines. In this way, the method contributes to the reduction of metal bit line coupling effect without any trade off of integrated circuit density by modifying the circuit layout of metal bit lines to a non-neighboring bit line arrangement in a memory array.

    摘要翻译： 公开了一种用于设计不相邻金属位线的电路布局以减少感测操作中的耦合效应的方法。 该方法包括提供具有顺序布置的多个位线的存储器阵列，其中每两个相邻位线在存储器阵列中的存储器单元的感测操作中配对。 通过分配互相排列的第一对位线来创建第一实施例以产生非相邻位线布局。 通过将第二对位线中的一个插入到第一对位线中以在布局设计中分离第一对位线来呈现第二实施例。 该方法还包括收缩两个相邻非配对位线之间的布局空间。 以这种方式，通过将金属位线的电路布局修改为存储器阵列中的非相邻位线布置，该方法有助于减少金属位线耦合效应，而不会降低集成电路密度。

    Dual reference cell sensing scheme for non-volatile memory
    5.
    发明授权
    Dual reference cell sensing scheme for non-volatile memory 有权
    用于非易失性存储器的双参考单元感测方案

    公开(公告)号：US06845052B1

    公开(公告)日：2005-01-18

    申请号：US10250040

    申请日：2003-05-30

    申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

    发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Liang Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

    IPC分类号： G11C7/06 ,  G11C7/14 ,  G11C16/28 ,  G11C7/02

    CPC分类号： G11C7/14 ,  G11C7/062 ,  G11C16/28 ,  G11C2207/2227

    摘要： The present invention provides a dual reference cell sensing scheme for non-volatile memory. A high voltage reference cell and a low voltage reference cell are individually coupled to two sense amplifiers for providing two distinct reference voltages for comparison against the memory cell voltage. The output of the two sense amplifiers is further connected to a second stage sense amplifier to determine the status of the memory. The dual reference cell sensing scheme provides an increased sensing window which increases performance under low voltage application. The dual reference cell sensing scheme can be implemented by either voltage-based, current-based, or ground.

    摘要翻译： 本发明提供了一种用于非易失性存储器的双参考单元感测方案。 高电压参考单元和低电压参考单元分别耦合到两个读出放大器，用于提供用于与存储单元电压进行比较的两个不同的参考电压。 两个读出放大器的输出进一步连接到第二级读出放大器以确定存储器的状态。 双参考电池感测方案提供增加的感测窗口，其在低电压应用下增加性能。 双参考电池感测方案可以通过基于电压，基于电流或接地来实现。

    Apparatus and system for reading non-volatile memory with dual reference cells
    6.
    发明授权
    Apparatus and system for reading non-volatile memory with dual reference cells 有权
    用于读取具有双参考单元的非易失性存储器的装置和系统

    公开(公告)号：US06665216B1

    公开(公告)日：2003-12-16

    申请号：US10202245

    申请日：2002-07-23

    申请人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

    发明人： Hsin-Yi Ho ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Gin-Laing Chen ,  Wen-Chiao Ho ,  Ho-Chun Liou

    IPC分类号： G11C700

    CPC分类号： G11C16/28 ,  G11C7/062

    摘要： A system for reading data in a memory cell includes three comparators, each of which has two inputs. A first reference cell having a low reference voltage is coupled to one input of the first comparator. A second reference cell having a high reference voltage is coupled to one input of the second comparator. A memory cell having a memory cell voltage is coupled to the other input of the first and second comparators. One input of the third comparator is coupled to the first comparator's output signal, which includes a difference voltage between the memory cell voltage and the low reference voltage. The other input of the third comparator is coupled to the second comparator's output signal, which includes a difference voltage between the memory cell voltage and the high reference voltage. A method and apparatus for reading data in a memory cell also are described.

    摘要翻译： 用于读取存储器单元中的数据的系统包括三个比较器，每个比较器具有两个输入。 具有低参考电压的第一参考单元耦合到第一比较器的一个输入端。 具有高参考电压的第二参考单元耦合到第二比较器的一个输入端。 具有存储单元电压的存储单元耦合到第一和第二比较器的另一个输入端。 第三比较器的一个输入耦合到第一比较器的输出信号，其包括存储单元电压和低参考电压之间的差电压。 第三比较器的另一输入端耦合到第二比较器的输出信号，其包括存储单元电压和高参考电压之间的差电压。 还描述了一种用于在存储器单元中读取数据的方法和装置。

    Memory array architecture
    7.
    发明授权
    Memory array architecture 有权
    内存阵列架构

    公开(公告)号：US06421267B1

    公开(公告)日：2002-07-16

    申请号：US09840709

    申请日：2001-04-24

    申请人： Nai-Ping Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    发明人： Nai-Ping Kuo ,  Hsin-Yi Ho ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    IPC分类号： G11C1134

    CPC分类号： G11C16/3495 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/16

    摘要： A memory array architecture includes a plurality of memory cells formed into rows and columns. A plurality of bit lines is connected to the memory cells through select transistors. By disposing adjacent bit lines into different metal layers or alternatively interlocating adjacent bit lines, the coupling effect between bit lines can be effectively reduced, and thus can improve reading speed of memory while performing read operation.

    摘要翻译： 存储器阵列结构包括形成行和列的多个存储单元。 多个位线通过选择晶体管连接到存储单元。 通过将相邻的位线布置在不同的金属层中或者可选地相互位置相邻的位线，可以有效地减少位线之间的耦合效应，从而可以在执行读取操作时提高存储器的读取速度。

    Method and structure for testing embedded flash memory
    8.
    发明授权
    Method and structure for testing embedded flash memory 有权
    嵌入式闪存测试方法和结构

    公开(公告)号：US06396753B1

    公开(公告)日：2002-05-28

    申请号：US09826497

    申请日：2001-04-05

    申请人： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Tu-Shun Chen ,  Ho-Chun Liou

    发明人： Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Tu-Shun Chen ,  Ho-Chun Liou

    IPC分类号： G11C700

    CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2207/104

    摘要： A method and structure for testing embedded flash memory including a memory array and a logic element. A control transistor is disposed and is connected between a sense amplifier and an I/O buffer in the memory array, and a speed control pin connected to the logic element in one terminal is coupled to the gate terminal of the control transistor in the other terminal to switch the control transistor on or off. Turning off the control transistor after a test time by the speed control pin closes the channel between the sense amplifier and I/O buffer, and an output signal from the memory array to a test system connected to the logic element is detected with the test system to determine an access time of the memory array.

    摘要翻译： 一种用于测试包括存储器阵列和逻辑元件的嵌入式闪速存储器的方法和结构。 控制晶体管被设置并连接在存储器阵列中的读出放大器和I / O缓冲器之间，并且连接到一个端子中的逻辑元件的速度控制引脚耦合到另一个端子中的控制晶体管的栅极端子 开关控制晶体管。 通过速度控制引脚在测试时间后关闭控制晶体管，关闭读出放大器和I / O缓冲器之间的通道，并从测试系统检测到从存储器阵列到连接到逻辑元件的测试系统的输出信号 以确定存储器阵列的访问时间。

    Method for tracking metal bit line coupling effect
    9.
    发明授权
    Method for tracking metal bit line coupling effect 有权
    跟踪金属位线耦合效应的方法

    公开(公告)号：US06385097B1

    公开(公告)日：2002-05-07

    申请号：US09805192

    申请日：2001-03-14

    申请人： Kuo-Yu Liao ,  Han-Sung Chen ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    发明人： Kuo-Yu Liao ,  Han-Sung Chen ,  Chun-Hsiung Hung ,  Ho-Chun Liou

    IPC分类号： G11C700

    CPC分类号： G11C7/1051 ,  G11C7/06 ,  G11C7/14

    摘要： A method for tracking metal bit line coupling effect in sensing a signal received from an array cell within a memory array is disclosed. The method includes that a reference unit with a reference cell is provided, wherein the reference unit induces coupling effect. Then, the memory array and the reference unit are charged to generate a cell signal having coupling effect and a reference signal having coupling effect. Next, a sensing signal is generated from the difference of the cell signal and the reference signal, whereby the coupling effect is compensated. In the read-out operation of the present invention, because of the closeness of two adjacent metal bit lines, the coupling effect is induced in both memory array and reference unit at the same time, so that the coupling effect is compensated. Therefore, precise read-out operation of data stored in a memory cell is made possible, and the reliability of the device is improved by the present invention.

    摘要翻译： 公开了一种用于跟踪金属位线耦合效应以感测从存储器阵列内的阵列单元接收的信号的方法。 该方法包括提供具有参考单元的参考单元，其中参考单元引起耦合效应。 然后，对存储器阵列和参考单元进行充电以产生具有耦合效应的单元信号和具有耦合效应的参考信号。 接下来，从单元信号和参考信号的差产生感测信号，从而补偿耦合效果。 在本发明的读出操作中，由于两个相邻的金属位线的接近，同时在存储器阵列和参考单元两者中引起耦合效应，从而补偿耦合效应。 因此，存储在存储单元中的数据的精确读出操作成为可能，并且通过本发明提高了器件的可靠性。

    Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device
    10.
    发明授权
    Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device 失效
    在电可擦除和电可编程存储器件中修复场效应存储器单元的方法

    公开(公告)号：US5233562A

    公开(公告)日：1993-08-03

    申请号：US815945

    申请日：1991-12-30

    申请人： Tong-Chern Ong ,  Ho-Chun Liou ,  Gregory E. Atwood

    发明人： Tong-Chern Ong ,  Ho-Chun Liou ,  Gregory E. Atwood

    IPC分类号： G11C16/14 ,  G11C16/34 ,  G11C29/02 ,  G11C29/50

    CPC分类号： G11C16/3409 ,  G11C16/14 ,  G11C16/3404 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50 ,  G11C29/50004 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5006

    摘要： A method of reprogramming field-effect memory cells of a memory array of an electrically erasable flash memory device is described. Each cell has a drain, a source, and a control gate. The drains of the cells are electrically connected to a bit line of the memory array. The cells are programmed and erased. The cells are repaired by grounding the sources and the control gates and taking the bit line to a predetermined potential. The memory array is selectively programmed. Other embodiments include repairing field-effect memory cells connected to a source line or part of a word line. Verification may be done between the repair step and selectively programming step.

    摘要翻译： 描述了重新编程电可擦除闪存器件的存储器阵列的场效应存储器单元的方法。 每个单元都有漏极，源极和控制栅极。 电池的漏极电连接到存储器阵列的位线。 单元被编程和擦除。 通过使源极和控制栅极接地并将位线置于预定电位来修复电池。 存储器阵列被有选择地编程。 其他实施例包括修复连接到源线或字线的一部分的场效应存储器单元。 可以在修复步骤和选择性编程步骤之间进行验证。