公开(公告)号：US20050111354A1

公开(公告)日：2005-05-26

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/24 ,  H04L12/26

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US06822486B1

公开(公告)日：2004-11-23

申请号：US10635968

申请日：2003-08-07

申请人： Matthew E. King ,  Peichun Liu ,  David Mui ,  Jieming Qi

发明人： Matthew E. King ,  Peichun Liu ,  David Mui ,  Jieming Qi

IPC分类号： H03K1700

CPC分类号： H04J3/047

摘要： In a first aspect, a method is provided for selecting a signal from a plurality of signals. The method includes the steps of (1) providing a plurality of multiplexers, each multiplexer configured to selectively output one of a plurality of signals input by the multiplexer using an output of the multiplexer; (2) selecting an input signal from one of the plurality of multiplexers to output; (3) outputting the selected input signal from the output of the one of the plurality of multiplexers; (4) forcing the outputs of the other of the plurality of multiplexers to a predetermined logic state; and (5) combining the outputs of the plurality of multiplexers so as to output the selected input signal. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供一种用于从多个信号中选择信号的方法。 该方法包括以下步骤：（1）提供多个复用器，每个多路复用器被配置为使用多路复用器的输出来选择性地输出由多路复用器输入的多个信号中的一个信号; （2）选择来自多个多路复用器中的一个的输入信号进行输出; （3）从所述多个复用器中的一个的输出端输出所选择的输入信号; （4）将所述多个复用器中的另一个的输出强制为预定的逻辑状态; 以及（5）组合多个复用器的输出以输出所选择的输入信号。 提供了许多其他方面。

公开(公告)号：US08483227B2

公开(公告)日：2013-07-09

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/56

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US08611368B2

公开(公告)日：2013-12-17

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/43 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

公开(公告)号：US20110246695A1

公开(公告)日：2011-10-06

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： G06F12/00

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20050138055A1

公开(公告)日：2005-06-23

申请号：US10738721

申请日：2003-12-17

申请人： Glen Handlogten ,  Peichun Liu ,  Jieming Qi

发明人： Glen Handlogten ,  Peichun Liu ,  Jieming Qi

IPC分类号： G06F13/37 ,  G06F17/00

CPC分类号： G06F13/37

摘要： A method and apparatus are provided for efficiently operating a round robin arbitration system in a given computer system. The system utilizes a series of banks of requesters and pointer. The banks of requesters and pointers operate on sequential AND-OR-Inverter/OR-AND-Inverter (AOI/OAI) logic to advance the pointer and efficiently select those requestors with pending requests. The use of the AOI/OAI logic circuitry in the banks of requestors and pointers allows for efficient selection and minimization of complex circuitry reducing the overall circuit area.

摘要翻译： 提供了一种用于在给定的计算机系统中有效地操作循环仲裁系统的方法和装置。 该系统使用一系列请求者和指针。 请求者和指针组按顺序的和/或 - 逆变器/或 - 和 - 反相器（AOI / OAI）逻辑运行，以推进指针，并有效地选择具有未决请求的请求者。 在请求者和指针库中使用AOI / OAI逻辑电路允许有效选择和最小化复杂电路，从而减小整个电路面积。

公开(公告)号：US20080065855A1

公开(公告)日：2008-03-13

申请号：US11531293

申请日：2006-09-13

申请人： Matthew E. King ,  Peichun P. Liu ,  David Mui ,  Mydung N. Pham ,  Jieming Qi ,  Thuong Q. Truong

发明人： Matthew E. King ,  Peichun P. Liu ,  David Mui ,  Mydung N. Pham ,  Jieming Qi ,  Thuong Q. Truong

IPC分类号： G06F12/00 ,  G06F13/28

CPC分类号： G06F13/28 ,  G06F12/1045 ,  G06F12/1081 ,  G06F12/145

摘要： A memory management unit (MMU) performs address translation and protection using a segment table and page table model. Each DMA queue entry may include a MMU-miss dependency flag. The DMA issue mechanism uses the MMU-miss dependency flag to block the issue of commands that are known to result in a translation miss. However, the direct memory access engine does not block subsequent DMA commands from being issued until they receive a translation miss. When the MMU completes processing of a miss, the MMU sends a miss clear signal to the DMA control unit to reset all MMU-miss dependency flags. When the MMU sends a miss clear signal, the DMA control unit will reset all DMA queue entries with MMU-miss dependency flags set. DMA commands in the DMA queue that were blocked from issue by the MMU-miss dependency flag may now be selected by the DMA control unit for issue.

摘要翻译： 存储器管理单元（MMU）使用段表和页表模型执行地址转换和保护。 每个DMA队列条目可以包括MMU-miss依赖标志。 DMA问题机制使用MMU-miss依赖标志来阻止已知导致翻译缺失的命令的问题。 然而，直接存储器访问引擎不会阻止随后的DMA命令被发出，直到它们接收到转换未命中。 当MMU完成未命中的处理时，MMU向DMA控制单元发送未命中清除信号，以复位所有MMU-miss依赖标志。 当MMU发送未命中清除信号时，DMA控制单元将重置所有设置了MMU-miss依赖标志的DMA队列条目。 DMA控制单元现在可以由DMA控制单元选择DMA队列中的DMA命令，由MMU-miss依赖标志阻止发布。

公开(公告)号：US20070083680A1

公开(公告)日：2007-04-12

申请号：US11246585

申请日：2005-10-07

申请人： Matthew Edward King ,  Peichun Peter Lui ,  David Mui ,  Jieming Qi

发明人： Matthew Edward King ,  Peichun Peter Lui ,  David Mui ,  Jieming Qi

IPC分类号： G06F13/28

CPC分类号： G06F12/1081 ,  G06F13/28

摘要： A system and method for improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.

摘要翻译： 提出了一种用于改进DMAC转换机制的系统和方法。 DMA命令根据DMA命令的传输大小和计算机系统一次传输的数据量“展开”。 对于第一个DMA请求，DMA队列请求内存管理单元执行地址转换。 DMA队列从MMU接收实际页码，并且在随后的发布请求中，DMA队列向总线接口单元提供实际页号，而不访问MMU，直到传输跨进下一页。 在每个DMA请求之后，滚动逻辑会递减DMA命令的传输大小，确定是否已经达到新的页面，确定DMA命令是否完成，并将后续的DMA请求的回写信息发送到DMA队列。

公开(公告)号：US07644198B2

公开(公告)日：2010-01-05

申请号：US11246585

申请日：2005-10-07

申请人： Matthew Edward King ,  Peichun Peter Lui ,  David Mui ,  Jieming Qi

发明人： Matthew Edward King ,  Peichun Peter Lui ,  David Mui ,  Jieming Qi

IPC分类号： G06F13/28 ,  G06F3/00 ,  G06F13/00

CPC分类号： G06F12/1081 ,  G06F13/28

摘要： An improved DMAC translation mechanism is presented. DMA commands are “unrolled” based upon the transfer size of the DMA command and the amount of data that a computer system transfers at one time. For the first DMA request, a DMA queue requests a memory management unit to perform an address translation. The DMA queue receives a real page number from the MMU and, on subsequent rollout requests, the DMA queue provides the real page number to a bus interface unit without accessing the MMU until the transfer crosses into the next page. Rollout logic decrements the DMA command's transfer size after each DMA request, determines whether a new page has been reached, determines if the DMA command is completed, and sends write back information to the DMA queue for subsequent DMA requests.

摘要翻译： 提出了改进的DMAC翻译机制。 DMA命令根据DMA命令的传输大小和计算机系统一次传输的数据量“展开”。 对于第一个DMA请求，DMA队列请求内存管理单元执行地址转换。 DMA队列从MMU接收实际页码，并且在随后的发布请求中，DMA队列向总线接口单元提供实际页号，而不访问MMU，直到传输跨进下一页。 在每个DMA请求之后，滚动逻辑会递减DMA命令的传输大小，确定是否已经达到新的页面，确定DMA命令是否完成，并将后续的DMA请求的回写信息发送到DMA队列。

公开(公告)号：US08201112B2

公开(公告)日：2012-06-12

申请号：US12129522

申请日：2008-05-29

申请人： David William Boerstler ,  Jieming Qi

发明人： David William Boerstler ,  Jieming Qi

IPC分类号： G06F17/50

CPC分类号： H03H11/405 ,  H03H11/1217

摘要： A design structure of a circuit for managing voltage swings across FETs comprising a reference precision resistor, a first and second FET, wherein a gate of the first FET is tied to a gate of the second FET, wherein a drain to source resistance of the second FET is substantially equal to or is a multiple of a resistance of the reference precision resistor, and wherein a gate voltage of the second FET is applied to a gate of the first FET to set a bias point of the first FET, and a third FET cascoded to the first FET, wherein a source of the first FET is coupled to the drain of the third FET to extend a voltage range in which respective gate voltages of the first and third FETs maintain a linear relationship with respective drain to source voltages of the first and third FETs.

摘要翻译： 一种用于管理跨FET的电压摆动的电路的设计结构，包括参考精密电阻器，第一和第二FET，其中第一FET的栅极连接到第二FET的栅极，其中第二FET的漏极 - 源极电阻 FET基本上等于或者是参考精密电阻器的电阻的倍数，并且其中第二FET的栅极电压被施加到第一FET的栅极以设置第一FET的偏置点，并且第三FET 级联到第一FET，其中第一FET的源极耦合到第三FET的漏极，以扩展电压范围，其中第一和第三FET的相应栅极电压与相应的漏极到源极电压保持线性关系 第一和第三FET。