公开(公告)号：US20050111354A1

公开(公告)日：2005-05-26

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Johns ,  Matthew King ,  Peichun Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/24 ,  H04L12/26

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US08483227B2

公开(公告)日：2013-07-09

申请号：US10718302

申请日：2003-11-20

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/56

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US08611368B2

公开(公告)日：2013-12-17

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： H04L12/43 ,  H04L12/28

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

公开(公告)号：US20110246695A1

公开(公告)日：2011-10-06

申请号：US13162917

申请日：2011-06-17

申请人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

发明人： Shigehiro Asano ,  Charles Ray Johns ,  Matthew Edward King ,  Peichun Peter Liu ,  David Mui ,  Jieming Qi

IPC分类号： G06F12/00

CPC分类号： H04L41/0896

摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.

摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。

公开(公告)号：US20050165987A1

公开(公告)日：2005-07-28

申请号：US10764626

申请日：2004-01-26

申请人： Shigehiro Asano ,  Peichun Liu ,  David Mui

发明人： Shigehiro Asano ,  Peichun Liu ,  David Mui

IPC分类号： G06F13/362 ,  G06F13/14 ,  G06F13/36

CPC分类号： G06F13/3625

摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

摘要翻译： 用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。 一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。 处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。 整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。 整形监视器根据其相对优先级向处理器分配插槽。 首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。

公开(公告)号：US07107376B2

公开(公告)日：2006-09-12

申请号：US10764626

申请日：2004-01-26

申请人： Shigehiro Asano ,  Peichun Peter Liu ,  David Mui

发明人： Shigehiro Asano ,  Peichun Peter Liu ,  David Mui

IPC分类号： G06F13/362 ,  G06F13/372

CPC分类号： G06F13/3625

摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

摘要翻译： 用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。 一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。 处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。 整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。 整形监视器根据其相对优先级向处理器分配插槽。 首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。

公开(公告)号：US20070168538A1

公开(公告)日：2007-07-19

申请号：US11716845

申请日：2007-03-12

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Harm Hofstee ,  Martin Hopkins ,  Charles Johns ,  James Kahle ,  Shigehiro Asano ,  Atsushi Kunimatsu

IPC分类号： G06F15/16

CPC分类号： G06F9/4862 ,  G06F15/16 ,  H04L29/06027 ,  H04L63/168 ,  H04L67/10 ,  H04L67/34

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

公开(公告)号：US20050028015A1

公开(公告)日：2005-02-03

申请号：US10631537

申请日：2003-07-31

申请人： Shigehiro Asano ,  Jeffrey Brown ,  Michael Day ,  Charles Johns ,  James Kahle ,  Alvan Ng ,  Michael Wang ,  Thuong Truong

发明人： Shigehiro Asano ,  Jeffrey Brown ,  Michael Day ,  Charles Johns ,  James Kahle ,  Alvan Ng ,  Michael Wang ,  Thuong Truong

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F12/0831 ,  G06F12/1027 ,  G06F2212/1028 ,  Y02D10/13

摘要： A component of a microprocessor-based data processing system, which includes features for regulating power consumption in snoopable components and has gating off memory coherency properties, is determined to be in a relatively inactive state and is transitioned to a non-snoopable low power mode. Then, when a snoop request occurs, a retry protocol is sent in response to the snoop request. In conjunction with the retry protocol, a signal is sent to bring the component into snoopable mode. When the retry snoop is requested, the component is in full power mode and can properly respond to the snoop request. After the snoop request has been satisfied, the component again enters into a low power mode. Therefore, the component is able to enter into a low power mode in between snoops

摘要翻译： 基于微处理器的数据处理系统的一个组件，其包括用于调节可窥探组件中的功耗并具有门控存储器一致性属性的特征，被确定为处于相对不活动状态，并且转换到不可窥探的低功率模式。 然后，当侦听请求发生时，响应于窥探请求发送重试协议。 结合重试协议，发送信号使组件进入窥探模式。 当请求重试监听时，组件处于全功率模式，并可以正常响应窥探请求。 在snoop请求已满足后，组件再次进入低功耗模式。 因此，该组件能够在两个snoops之间进入低功耗模式

公开(公告)号：US08812774B2

公开(公告)日：2014-08-19

申请号：US13217461

申请日：2011-08-25

申请人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

发明人： Shigehiro Asano ,  Shinichi Kanno ,  Kazuhiro Fukutomi ,  Akira Yamaga

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F11/1068

摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.

摘要翻译： 根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子 接收单元; 发电机组; 第二个表 和书写单位。 第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。 生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。 在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。 当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。

公开(公告)号：US08612824B2

公开(公告)日：2013-12-17

申请号：US13038804

申请日：2011-03-02

申请人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

发明人： Kazumasa Yamamoto ,  Shinichi Kanno ,  Shigehiro Asano ,  Hiroyuki Nagashima

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G11C16/3418 ,  G11C16/00 ,  G11C29/028

摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.

摘要翻译： 半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。