公开(公告)号：US5012448A

公开(公告)日：1991-04-30

申请号：US220976

申请日：1988-07-15

申请人： Shigeki Matsuoka ,  Hiizu Okubo ,  Daisuke Kosaka

发明人： Shigeki Matsuoka ,  Hiizu Okubo ,  Daisuke Kosaka

IPC分类号： G11C7/14 ,  G11C11/56 ,  G11C16/28 ,  H01L27/112

CPC分类号： G11C11/5642 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5692 ,  G11C16/28 ,  G11C7/14 ,  H01L27/112 ,  G11C2211/5634 ,  G11C7/06

摘要： A multilevel sense circuit includes a memory MOSFET having one of at least two different current carrying states and a pair of reference MOSFETs one of which has one of the two current carrying states and the other of which has the other current carrying state. A first current supplying circuit is connected to the memory MOSFET for supplying a predetermined amount of current thereto when the memory MOSFET is activated. A second current supplying circuit is connected to the pair of reference MOSFETs and also to the first current supplying circuit, such that twice the aforementioned predetermined amount of current is supplied to the pair of reference MOSFETs when the memory MOSFET is activated. A multilevel semiconductor memory device includes a MOSFET having a channel whose width is varyingly set by providing a non-inverting region in a selected area of the channel by ion implantation.

摘要翻译： 多电平检测电路包括具有至少两个不同载流状态中的一个的存储器MOSFET和一对参考MOSFET，其中一个参考MOSFET具有两个载流状态之一，另一个具有另一个载流状态。 当存储器MOSFET被激活时，第一电流供应电路连接到存储器MOSFET，用于向其提供预定量的电流。 第二电流供应电路连接到一对参考MOSFET并且还连接到第一电流供应电路，使得当存储器MOSFET被激活时，上述预定量的电流被提供给一对参考MOSFET。 多级半导体存储器件包括MOSFET，其具有通过离子注入在沟道的选定区域中提供非反相区域而使宽度变化地设定的沟道。

公开(公告)号：US5291453A

公开(公告)日：1994-03-01

申请号：US17843

申请日：1993-02-16

申请人： Hideyuki Aota ,  Hiizu Okubo

发明人： Hideyuki Aota ,  Hiizu Okubo

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C8/16 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C7/12 ,  G11C8/16

摘要： A memory apparatus includes a memory cell array in which a plurality of memory cells are arranged in a matrix formation and divided into blocks, a writing part for serially writing data to the memory cell array through a set of writing bit lines, each of the writing bit lines connected to one of the blocks, a reading part for serially reading the data from the memory cells of the memory cell array through a set of reading bit lines, each of the reading bit lines connected to one of the blocks, and a set of precharging units each for presetting one of the reading bit lines to a prescribed voltage when data is read from one of the blocks of the memory cell array. In this apparatus, when a first reading cycle is carried out to read data from one memory cell of a first block and a second reading cycle is consecutively carried out to read data from one memory cell of a second block lying consecutively to the first block, one of the precharging units presets the reading bit line connected to the second block to the prescribed voltage during the first reading cycle before the data is read from the memory cell of the second block.

摘要翻译： 一种存储装置，包括存储单元阵列，其中多个存储单元以矩阵形式排列并分成多个块;写入部，用于通过一组写入位线将数据串行地写入存储单元阵列，每个写入 连接到其中一个块的位线，读取部分，用于通过一组读取位线，连接到一个块的每个读取位线，以及一个集合来串行地从存储单元阵列的存储器单元读取数据 的预充电单元，每个用于在从存储单元阵列的一个块读取数据时，将读取位线之一预设为规定电压。 在该装置中，当执行第一读取周期以从第一块的一个存储器单元读取数据，并且连续执行第二读取周期以从连续向第一块的第二块的一个存储器单元读取数据时， 在从第二块的存储单元读取数据之前，预充电单元之一将在第一读取周期期间将连接到第二块的读取位线预设为规定电压。

公开(公告)号：US5737273A

公开(公告)日：1998-04-07

申请号：US630929

申请日：1996-04-05

申请人： Hideo Fujiwara ,  Seiji Yamanaka ,  Toshihisa Nagata ,  Hiizu Okubo

发明人： Hideo Fujiwara ,  Seiji Yamanaka ,  Toshihisa Nagata ,  Hiizu Okubo

IPC分类号： G11C7/06 ,  H01L27/10

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A state control portion causes a sense amplifier portion to be at an active state and for causing the sense amplifier to be at an inactive state. A feedback portion causes the control device to causing the sense amplifier portion to be in the inactive state when a path is formed between a power source and a ground in the sense amplifier. A latch portion holds an output of the sense amplifier output when the path is formed. The state control portion comprises a first transistor acting as a switching device. The feedback portion produces a control signal using an output of the sense amplifier portion and a clock signal obtained from a detection circuit, and supplies the control signal to the first transistor. A second transistor for precharging is connected between the first transistor and the power source.

公开(公告)号：US5729499A

公开(公告)日：1998-03-17

申请号：US790953

申请日：1997-01-29

申请人： Hideo Fujiwara ,  Seiji Yamanaka ,  Toshihisa Nagata ,  Hiizu Okubo

发明人： Hideo Fujiwara ,  Seiji Yamanaka ,  Toshihisa Nagata ,  Hiizu Okubo

IPC分类号： G11C7/06 ,  G11C11/40

CPC分类号： G11C7/067 ,  G11C7/065

摘要： A state control portion causes a sense amplifier portion to be at an active state and for causing the sense amplifier to be at an inactive state. A feedback portion causes the control device to causing the sense amplifier portion to be in the inactive state when a path is formed between a power source and a ground in the sense amplifier. A latch portion holds an output of the sense amplifier output when the path is formed. The state control portion comprises a first transistor acting as a switching device. The feedback portion produces a control signal using an output of the sense amplifier portion and a clock signal obtained from a detection circuit, and supplies the control signal to the first transistor. A second transistor for precharging is connected between the first transistor and the power source.

摘要翻译： 状态控制部分使得感测放大器部分处于活动状态并且使感测放大器处于非活动状态。 当在感测放大器中的电源和地之间形成路径时，反馈部分使得控制装置使感测放大器部分处于非活动状态。 当形成路径时，锁存部分保持读出放大器输出的输出。 状态控制部分包括用作开关装置的第一晶体管。 反馈部分使用读出放大器部分的输出和从检测电路获得的时钟信号产生控制信号，并将控制信号提供给第一晶体管。 用于预充电的第二晶体管连接在第一晶体管和电源之间。

公开(公告)号：US5285069A

公开(公告)日：1994-02-08

申请号：US795834

申请日：1991-11-21

申请人： Mitsuo Kaibara ,  Hiizu Okubo ,  Takako Maruyama ,  Seiji Yamanaka ,  Hideyuki Aota

发明人： Mitsuo Kaibara ,  Hiizu Okubo ,  Takako Maruyama ,  Seiji Yamanaka ,  Hideyuki Aota

IPC分类号： H01L27/118 ,  H01L29/76 ,  H01L23/62 ,  H01L27/10 ,  H01L27/11

CPC分类号： H01L27/11807 ,  Y10S257/903

摘要： A semiconductor integrated circuit apparatus has a basic cell region formed by arranging a plurality of basic cells each including a MOS transistor in longitudinal and transversal directions. The MOS transistor has source-drain section diffusive regions formed on a semiconductor substrate, and a gate electrode formed on a channel region between these source-drain section diffusive regions through a gate insulating film. One portion or all of the channel region of at least one MOS transistor within the basic cell region has an impurity concentration different from that in the channel region of another MOS transistor of the same conductivity type within the same basic cell. For example, a threshold voltage in the channel region of a MOS transistor is increased until about 6 volts by implanting ions into the channel region. No MOS transistor is operated at a power voltage such as 5 volts and separates MOS transistors on both sides thereof from each other. Wiring is formed on the MOS transistor and the gate electrode is used as the wiring, thereby improving wiring efficiency.

摘要翻译： 半导体集成电路装置具有通过在纵向和横向上布置包括MOS晶体管的多个基本单元而形成的基本单元区域。 MOS晶体管具有形成在半导体衬底上的源极 - 漏极部扩散区域，以及通过栅极绝缘膜形成在这些源 - 漏部扩散区域之间的沟道区上的栅电极。 在基本单元区域内的至少一个MOS晶体管的沟道区域的一部分或全部具有与同一基本单元内的相同导电类型的另一个MOS晶体管的沟道区域中的杂质浓度不同的杂质浓度。 例如，MOS晶体管的通道区域中的阈值电压通过将离子注入沟道区而增加直到约6伏特。 没有MOS晶体管在诸如5伏的电源电压下操作，并且将其两侧的MOS晶体管彼此分离。 在MOS晶体管上形成接线，并且使用栅电极作为布线，从而提高布线效率。

公开(公告)号：US5740108A

公开(公告)日：1998-04-14

申请号：US762450

申请日：1996-12-09

申请人： Hiizu Okubo

发明人： Hiizu Okubo

IPC分类号： G11C8/10 ,  G11C17/12 ,  G11C17/18

CPC分类号： G11C8/10 ,  G11C17/123

摘要： A semiconductor memory device which has a reduced current consumption. A memory block includes a pair of memory cell columns each of which includes a plurality of memory cells connected in series, the memory cell columns being connected in series in a column direction along which the memory cells are arranged, a position of each of the memory cells being indicated by address data comprising first address data and second address data. Each of a plurality of word lines is connected to a corresponding one of the memory cells included in the memory block on a one to one basis. A memory cell column selection decoder selects one of the memory cell columns based on the first address data. A word line selection decoder selects one of the word lines based on the second address data and a control signal which is logically equivalent to the first address data. Additional memory blocks may be arranged in a row direction perpendicular to the column direction. Each of the bit lines may be connected to a data line via a switch unit so that one of the bit lines is precharged via the data line when the switch unit is conductive.

摘要翻译： 一种具有降低的电流消耗的半导体存储器件。 存储块包括一对存储单元列，每个存储单元列包括串联连接的多个存储单元，存储单元列沿存储单元排列的列方向串联连接，每个存储器的位置 小区由包括第一地址数据和第二地址数据的地址数据指示。 多个字线中的每一个一一对应地连接到包括在存储块中的存储单元中的对应的一个。 存储单元列选择解码器基于第一地址数据选择一个存储单元列。 字线选择解码器基于第二地址数据和在逻辑上等同于第一地址数据的控制信号来选择字线之一。 附加的存储器块可以沿垂直于列方向的行方向布置。 每个位线可以经由开关单元连接到数据线，使得当开关单元导通时，位线之一经由数据线被预充电。

公开(公告)号：US5495444A

公开(公告)日：1996-02-27

申请号：US275233

申请日：1994-07-14

申请人： Hiizu Okubo ,  Hideyuki Aota

发明人： Hiizu Okubo ,  Hideyuki Aota

IPC分类号： G11C11/41 ,  G06F5/10 ,  G11C8/16 ,  G11C11/401 ,  G11C7/00

CPC分类号： G06F5/10 ,  G11C8/16

摘要： A semiconductor memory device having a small chip area is provided to reduce a manufacturing cost. The semiconductor memory device has memory unit comprising memory cells arranged in a matrix comprising n rows and m columns, where m.gtoreq.2 and n.gtoreq.1, each of the memory cells having a single port and being capable of storing a single word of data comprising at least one bit, the memory cells arranged in a single column forming a memory cell block. The semiconductor memory device selects one set of two memory cells, one from an arbitrary memory cell block and the other from a different memory cell block. A reading operation performed and a writing operation for the set of two memory cells are performed during the same cycle. Another set of two memory cells are selected by a selecting unit, when the reading operation and the writing operation for one cycle are completed, for performing another cycle of the reading operation and the writing operation, the reading operation and the writing operation being repeated for a predetermined number of cycles.

摘要翻译： 提供具有小芯片面积的半导体存储器件以降低制造成本。 半导体存储器件具有存储单元，该存储器单元包括排列成n行m列的矩阵的存储单元，其中m≥2且n> / = 1，每个存储器单元具有单个端口并且能够存储单个 包含至少一个位的数据字，存储单元布置在形成存储单元块的单列中。 半导体存储器件选择一组两个存储器单元，一组来自任意存储单元块，另一组来自不同存储单元块。 在同一周期中执行读取操作和对两组存储器单元的写入操作。 另一组两个存储单元由选择单元选择，当一个周期的读取操作和写入操作完成时，为了执行读取操作和写入操作的另一个周期，重复读取操作和写入操作 预定数量的循环。

公开(公告)号：US5029135A

公开(公告)日：1991-07-02

申请号：US480583

申请日：1990-02-15

申请人： Hiizu Okubo

发明人： Hiizu Okubo

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C7/14 ,  G11C8/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/417

CPC分类号： G11C7/12 ,  G11C7/14 ,  G11C8/18

摘要： A semiconductor memory apparatus of an internal synchronization type uses a clock signal generated by detecting a change in address or control signal as an internal synchronization signal. The apparatus includes a dummy memory cell for fixing data thereto in advance; a precharging circuit for precharging an internal memory cell and the dummy cell; a precharge completion detector for detecting the completion of the precharging operation when a dummy bit line from the dummy cell attains a predetermined voltage level by the precharging operation, the precharge completion detector transmitting a signal for completing the precharging operation with respect to the precharging circuit; and a device for reading or writing data through a bit line to the memory cell by the completion of the precharging operation by the precharge completion detector.

摘要翻译： 内部同步型的半导体存储装置使用通过检测地址或控制信号的变化而产生的时钟信号作为内部同步信号。 该装置包括用于预先固定数据的虚拟存储单元; 用于对内部存储单元和所述虚拟单元进行预充电的预充电电路; 预充电完成检测器，用于当来自虚拟单元的虚拟位线通过预充电操作达到预定电压电平时，检测预充电操作的完成，预充电完成检测器发送用于完成对预充电电路的预充电操作的信号; 以及通过预充电完成检测器完成预充电操作，通过位线将数据读取或写入存储单元的装置。