公开(公告)号：US5640387A

公开(公告)日：1997-06-17

申请号：US542652

申请日：1995-10-13

申请人： Shigeki Takahashi ,  Tsuyoshi Ueshima ,  Kazuo Tanaka ,  Eiji Shimose

发明人： Shigeki Takahashi ,  Tsuyoshi Ueshima ,  Kazuo Tanaka ,  Eiji Shimose

IPC分类号： H04J3/06 ,  H04J3/00 ,  H04J3/08 ,  H04J3/12 ,  H04L7/00 ,  H04Q3/42 ,  H04Q3/52 ,  H04Q11/04 ,  H04J3/02

CPC分类号： H04J3/0688 ,  H04J3/08 ,  H04J3/12 ,  H04Q11/0478 ,  H04J2203/0005 ,  H04J2203/0041 ,  H04J2203/0046 ,  H04J3/0647 ,  H04L7/0083

摘要： A high-speed signal input to and output from a high-speed optical interface part connected to an optical fiber transmission line is switched to different lines such that the switching is conducted by cross connect parts on an arbitrary basis. The high-speed signal is separated so as to obtain the low-speed signal. The low-speed signal output from the cross connect parts is separated so as to obtain the subscriber signal by signal terminal parts. Call connections are conducted for each subscriber by a time slot interchange part, whereupon a subscriber interface part performs analog-to-digital and digital-to-analog conversion so as to serve as an interface for a subscriber.

摘要翻译： 输入到与光纤传输线连接的高速光接口部分输出的高速信号被切换到不同的线路，从而以任意的方式通过交叉连接部分进行切换。 高速信号被分离以获得低速信号。 从交叉连接部分输出的低速信号被分离，以便通过信号端子部分获得用户信号。 通过时隙交换部分为每个用户进行呼叫连接，由此用户接口部分执行模数转换和数模转换，以便作为用户的接口。

公开(公告)号：US6160816A

公开(公告)日：2000-12-12

申请号：US902277

申请日：1997-07-29

申请人： Kazuo Tanaka ,  Eiji Shimose

发明人： Kazuo Tanaka ,  Eiji Shimose

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04J3/07 ,  H04J3/12 ,  H04Q3/42 ,  H04Q11/04

CPC分类号： H04J3/07 ,  H04J3/0685 ,  H04J3/12 ,  H04Q11/0471 ,  H04Q2213/13103 ,  H04Q2213/13214

摘要： A first group of asynchronous clock converters effect the conversion between a DNE clock and an RDT clock to which DS-0 data and signalling data are synchronized, for the data items which are transferred between a cross-connector and a DNE. A second group of asynchronous clock converters effect the conversion between a CPE clock and the RDT clock to which DS-0 data and signalling data are synchronized, for the data items which are transferred between the cross-connector and a CPE. As a result, cross-connect processes based on the single RDT clock are realized, and loop timings are guaranteed for the DNE and the CPE.

摘要翻译： 第一组异步时钟转换器对于在交叉连接器和DNE之间传输的数据项，会影响DNE时钟与DS-0数据和信令数据同步的RDT时钟之间的转换。 第二组异步时钟转换器影响在交叉连接器和CPE之间传输的数据项之间的CPE时钟与DS-0数据和信号数据同步的RDT时钟之间的转换。 因此，实现了基于单个RDT时钟的交叉连接过程，并为DNE和CPE保证了循环定时。

公开(公告)号：US08973253B2

公开(公告)日：2015-03-10

申请号：US14074858

申请日：2013-11-08

申请人： Tatsuki Hirano ,  Kazuo Tanaka

发明人： Tatsuki Hirano ,  Kazuo Tanaka

IPC分类号： H01C17/00 ,  H01C17/245

CPC分类号： H01C17/006 ,  H01C17/245

摘要： The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus for manufacturing metal plate chip resistors including cutting mold for cutting intermediate product strip transversely to obtain worked product chip, ohm meter for measuring the resistance of the worked product chip, control device having a calculating part for performing a calculation using the resistance measured by the ohm meter to work out a width in which the strip is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjustor for making an adjustment so that the strip is to be cut transversely in the width obtained from the calculating part.

摘要翻译： 本发明的目的是提供一种通过简单的工艺制造具有相对较低电阻的金属板片式电阻器的方法和装置，其具有高精度和高产率。 该目的是通过用于制造金属板片电阻器的装置实现的，包括用于横向切割中间产品带的切割模具，以获得加工产品芯片，用于测量加工产品芯片的电阻的欧姆表，具有用于执行计算的计算部分的控制装置 由欧姆计测量的电阻以横向切割条的宽度，以获得期望电阻的加工产品芯片，以及用于进行调整的切割宽度调节器，使得条被切割 横向于从计算部分获得的宽度。

公开(公告)号：US08590141B2

公开(公告)日：2013-11-26

申请号：US13196078

申请日：2011-08-02

申请人： Tatsuki Hirano ,  Kazuo Tanaka

发明人： Tatsuki Hirano ,  Kazuo Tanaka

IPC分类号： H01C17/00

CPC分类号： H01C17/006 ,  H01C17/245

摘要： The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus 10 for manufacturing metal plate chip resistors including cutting mold 21 for cutting intermediate product strip 14 transversely to obtain worked product chip 16a, ohm meter 22 for measuring the resistance of the worked product chip 16a, control device 23 having a calculating part for performing a calculation using the resistance measured by the ohm meter 22 to work out a width in which the strip 14 is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjusting means 26, 27 for making an adjustment so that the strip 14 is to be cut transversely in the width obtained from the calculating part.

摘要翻译： 本发明的目的是提供一种通过简单的工艺制造具有相对较低电阻的金属板片式电阻器的方法和装置，其具有高精度和高产率。 该目的是通过用于制造金属板片式电阻器的装置10实现的，包括用于横向切割中间产品条带14的切割模具21，以获得加工产品芯片16a，用于测量加工产品芯片16a的电阻的欧姆计22，具有 使用由欧姆计22测量的电阻进行计算的计算部分，以计算要横向切割条带14的宽度，以获得期望电阻的加工产品芯片;以及切割宽度调节装置26， 27，用于进行调整，使得条带14在从计算部分获得的宽度上横向切割。

公开(公告)号：US08584783B2

公开(公告)日：2013-11-19

申请号：US13531361

申请日：2012-06-22

申请人： Daisuke Saeki ,  Kazuo Tanaka

发明人： Daisuke Saeki ,  Kazuo Tanaka

IPC分类号： B62M27/02

CPC分类号： B62M7/02 ,  B62K19/30 ,  F02B33/32 ,  F02M35/162

摘要： A motorcycle includes a combustion engine (E) of a type, in which a cylinder block (34) protrudes upwardly from a crankcase (32), an air cleaner unit (42) for substantially purifying an air, and a supercharger (44) for taking a substantially purified air from the air cleaner unit (42) thereinto and supplying the air towards the combustion engine (E). The supercharger (44) is disposed rearwardly of the cylinder block (34) and the air cleaner unit (42) is disposed rearwardly thereof. Also, a surge tank (48) is disposed rearwardly upwardly of the cylinder block (34) of the combustion engine (E) and above the supercharger (44).

摘要翻译： 摩托车包括一种内燃机（E），其中气缸体（34）从曲轴箱（32）向上突出，用于基本上净化空气的空气滤清器单元（42），以及增压器（44），用于 从空气滤清器单元（42）中取出基本上净化的空气并将空气供给到内燃机（E）。 增压器（44）设置在气缸体（34）的后方，空气滤清器单元（42）设置在气缸体的后方。 此外，缓冲罐（48）设置在内燃机（E）的气缸体（34）的上方的上方并且位于增压器（44）的上方。

公开(公告)号：US20130049864A1

公开(公告)日：2013-02-28

申请号：US13589369

申请日：2012-08-20

申请人： Natsuki IKEHATA ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

发明人： Natsuki IKEHATA ,  Kazuo Tanaka ,  Takeo Toba ,  Masashi Arakawa

IPC分类号： H03F3/45

CPC分类号： G11C11/4091 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

摘要翻译： 差分放大电路的输出信号特性得到改善。 当输入数据信号为低电平时，流过第一晶体管的电流将减小，并且第一电阻器和第二电阻器之间的连接（节点）的电位将增加。 该电位被输入（负反馈）到第二晶体管的栅极，并且由于该栅极电位增加，所以在增加的方向上调节尾部电流量。 当输入数据信号为高电平时，第一晶体管的电流增加，因此节点处的电位降低。 因此，第二晶体管的栅极电位（负反馈）减小，并且沿着减小的方向调整尾电流量。 因此，在输入波形的上升和下降中，延迟时间相对于输出波形的差别分别减小。

公开(公告)号：US08173806B2

公开(公告)日：2012-05-08

申请号：US12282381

申请日：2007-03-14

申请人： Kazuo Tanaka ,  Yoshifumi Sato ,  Takafumi Yoshimura

发明人： Kazuo Tanaka ,  Yoshifumi Sato ,  Takafumi Yoshimura

IPC分类号： C07D239/72

CPC分类号： C07D239/88

摘要： In reacting an anthranilic acid derivative represented by the general formula (1), especially the anthranilic acid derivative selected from anthranilic acid, anthranilamide and anthranilate, with formamide, the reaction is attained under the condition of coexistence of acetic acid and a base as a catalyst in the reaction liquid, and it has made it possible to produce a quinazolin-4-one derivative represented by the general formula (2) and useful as a material for medicine intermediates, at high yield with no side production.

摘要翻译： 在使通式（1）表示的邻氨基苯甲酸衍生物，特别是选自邻氨基苯甲酸，邻氨基苯甲酰胺和邻氨基苯甲酸酯的邻氨基苯甲酸衍生物与甲酰胺反应时，在乙酸和碱作为催化剂共存的条件下反应 在反应液中，可以以高产率生产无副产物的由通式（2）表示的喹唑啉-4-酮衍生物作为医药中间体的材料。

公开(公告)号：US08139332B2

公开(公告)日：2012-03-20

申请号：US13095480

申请日：2011-04-27

申请人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

发明人： Kazuo Tanaka ,  Hiroyuki Mizuno ,  Rie Nishiyama ,  Manabu Miyamoto

IPC分类号： H02H3/20 ,  H01L23/60

CPC分类号： H03K3/356113 ,  H01L2924/0002 ,  H03K3/356104 ,  H01L2924/00

摘要： In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

摘要翻译： 在安装在使用多个高压和低压电源的集成电路装置中的电平转换电路中，提供到差分输入的输入。 在降压电路中，栅极和漏极之间以及栅极和源极之间未提供3.3 V的MOS晶体管使用薄的氧化物层。 在升高电路中，提供逻辑运算功能。

公开(公告)号：US20110271066A1

公开(公告)日：2011-11-03

申请号：US13179403

申请日：2011-07-08

申请人： Tatsuya NINOMIYA ,  Kazuo Tanaka

发明人： Tatsuya NINOMIYA ,  Kazuo Tanaka

IPC分类号： G06F12/00

CPC分类号： G06F12/0868 ,  G06F12/0811 ,  G06F2212/284

摘要： The present invention comprises a CHA 110 which transmits/receives data to/from an external device, a DKA 140 which transmits/receives data to/from an HDD unit 200, a primary cache unit 120 which has a primary cache memory 124, a secondary cache unit 130 which is installed between the primary cache unit 120 and the DKA 140 and has a secondary cache memory 134, a CCP 121 which stores write target data received by the CHA 110 in the primary cache memory 124, and a CCP 131 which stores the write target data in the secondary cache memory 134, and transfers the write target data stored in the secondary cache memory 134 to the DKA 140.

摘要翻译： 本发明包括向外部设备发送/接收数据的CHA 110，从HDD单元200发送/接收数据的DKA140，具有主高速缓存存储器124的主高速缓存单元120，辅助缓存单元120 高速缓存单元130安装在主缓存单元120和DKA 140之间，并且具有二级高速缓存存储器134，存储由CHA 110接收的写目标数据在一级高速缓冲存储器124中的CCP 121和存储 在二次高速缓存存储器134中的写入目标数据，并将存储在二次高速缓冲存储器134中的写入目标数据传送到DKA 140。

公开(公告)号：US08013656B2

公开(公告)日：2011-09-06

申请号：US12944898

申请日：2010-11-12

申请人： Yusuko Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

发明人： Yusuko Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

IPC分类号： H03L5/00

CPC分类号： H03K19/018521 ,  H01L27/0928 ,  H01L27/105 ,  H03K3/356113

摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

摘要翻译： 提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。 在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元 用于驱动主要大型缓冲区。 鉴于此，高电压被施加到电平转换器和预缓冲器电路。 通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。