利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.023 秒)

    Semicondutor integrated circuit device
    1.
    发明授权
    Semicondutor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08013656B2

    公开(公告)日：2011-09-06

    申请号：US12944898

    申请日：2010-11-12

    申请人： Yusuko Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    发明人： Yusuko Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018521 ,  H01L27/0928 ,  H01L27/105 ,  H03K3/356113

    摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

    摘要翻译： 提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。 在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元 用于驱动主要大型缓冲区。 鉴于此，高电压被施加到电平转换器和预缓冲器电路。 通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

    Semiconductor integrated circuit device
    2.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20060232307A1

    公开(公告)日：2006-10-19

    申请号：US11405541

    申请日：2006-04-18

    申请人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    发明人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    IPC分类号： H03B1/00

    CPC分类号： H03K19/018521 ,  H01L27/0928 ,  H01L27/105 ,  H03K3/356113

    摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

    摘要翻译： 提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。 在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元 用于驱动主要大型缓冲区。 鉴于此，高电压被施加到电平转换器和预缓冲器电路。 通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

    Semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07855590B2

    公开(公告)日：2010-12-21

    申请号：US12422712

    申请日：2009-04-13

    申请人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    发明人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018521 ,  H01L27/0928 ,  H01L27/105 ,  H03K3/356113

    摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

    摘要翻译： 提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。 在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元 用于驱动主要大型缓冲区。 鉴于此，高电压被施加到电平转换器和预缓冲器电路。 通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

    Semiconductor integrated circuit
    4.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20070019493A1

    公开(公告)日：2007-01-25

    申请号：US11452238

    申请日：2006-06-14

    申请人： Takeo Toba ,  Kazuo Tanaka ,  Shunsuke Toyoshima

    发明人： Takeo Toba ,  Kazuo Tanaka ,  Shunsuke Toyoshima

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C7/1066 ,  G11C11/4074

    摘要： The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven. In an output circuit of the second input/output circuit, a drive signal is generated by a level shifter in a manner similar to the above to drive second and third N-channel MOSFETs for generating an output signal having signal amplitude corresponding to the third power source voltage.

    摘要翻译： 本发明提供一种具有两种输入/输出电路的半导体集成电路，其实现了具有合理配置的更高速度和更高的封装密度。 半导体集成电路具有以第一电源电压工作的第一输入/输出电路，以及低于第一电源电压的第二电源电压运行的内部电路，以及在第三电源上运行的第二输入/输出电路 电压低于第一电源电压。 在第一输入/输出电路的输出电路中，对应于第二电源电压的信号幅度由电平移位器转换成对应于第一电源电压的信号幅度，以及P沟道MOSFET和N沟道MOSFET 驱动输出电路的构造。 在第二输入/输出电路的输出电路中，以与上述类似的方式由电平转换器产生驱动信号，以驱动第二和第三N沟道MOSFET，以产生具有对应于第三功率的信号幅度的输出信号 源电压。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    5.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20090195292A1

    公开(公告)日：2009-08-06

    申请号：US12422712

    申请日：2009-04-13

    申请人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    发明人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018521 ,  H01L27/0928 ,  H01L27/105 ,  H03K3/356113

    摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

    摘要翻译： 提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。 在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元 用于驱动主要大型缓冲区。 鉴于此，高电压被施加到电平转换器和预缓冲器电路。 通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。

    Semiconductor integrated circuit
    6.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07425845B2

    公开(公告)日：2008-09-16

    申请号：US11452238

    申请日：2006-06-14

    申请人： Takeo Toba ,  Kazuo Tanaka ,  Shunsuke Toyoshima

    发明人： Takeo Toba ,  Kazuo Tanaka ,  Shunsuke Toyoshima

    IPC分类号： H03K19/0185

    CPC分类号： G11C5/147 ,  G11C7/1066 ,  G11C11/4074

    摘要： The present invention provides a semiconductor integrated circuit having two kinds of input/output circuits realizing higher speed and higher packing density with rational configuration. The semiconductor integrated circuit has a first input/output circuit operating on a first power source voltage, an internal circuit operating on a second power source voltage lower than the first power source voltage, and a second input/output circuit operating on a third power source voltage lower than the first power source voltage. In an output circuit of the first input/output circuit, signal amplitude corresponding to the second power source voltage is converted to signal amplitude corresponding to the first power source voltage by a level shifter, and a P-channel MOSFET and an N-channel MOSFET constructing the output circuit are driven. In an output circuit of the second input/output circuit, a drive signal is generated by a level shifter in a manner similar to the above to drive second and third N-channel MOSFETs for generating an output signal having signal amplitude corresponding to the third power source voltage.

    摘要翻译： 本发明提供一种具有两种输入/输出电路的半导体集成电路，其实现了具有合理配置的更高速度和更高的封装密度。 半导体集成电路具有以第一电源电压工作的第一输入/输出电路，以及低于第一电源电压的第二电源电压运行的内部电路，以及在第三电源上运行的第二输入/输出电路 电压低于第一电源电压。 在第一输入/输出电路的输出电路中，对应于第二电源电压的信号幅度由电平移位器转换成对应于第一电源电压的信号幅度，以及P沟道MOSFET和N沟道MOSFET 驱动输出电路的构造。 在第二输入/输出电路的输出电路中，以与上述类似的方式由电平转换器产生驱动信号，以驱动第二和第三N沟道MOSFET，以产生具有对应于第三功率的信号幅度的输出信号 源电压。

    Semiconductor integrated circuit device having I/O circuitry for low voltage operation
    7.
    发明授权
    Semiconductor integrated circuit device having I/O circuitry for low voltage operation 有权
    具有用于低压操作的I / O电路的半导体集成电路器件

    公开(公告)号：US07532054B2

    公开(公告)日：2009-05-12

    申请号：US11405541

    申请日：2006-04-18

    申请人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    发明人： Yusuke Kanno ,  Kazuo Tanaka ,  Shunsuke Toyoshima ,  Takeo Toba

    IPC分类号： H03L5/00

    CPC分类号： H03K19/018521 ,  H01L27/0928 ,  H01L27/105 ,  H03K3/356113

    摘要： A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

    摘要翻译： 提供了包括能够以低成本进行低电压高速运行的I / O电路的半导体集成电路装置。 在I / O电路中，当I / O电压（例如3.3V）降低到预定电压（例如1.8V）时，导致速度劣化的部分是电平转换单元和预缓冲单元 用于驱动主要大型缓冲区。 鉴于此，高电压被施加到电平转换器和预缓冲器电路。 通过这样做，可以以低成本实现能够进行低电压高速操作的I / O电路。