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    Semiconductor device, method of manufacturing same and method of designing same
    3.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 失效
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US06953979B1

    公开(公告)日：2005-10-11

    申请号：US09466934

    申请日：1999-12-20

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor device, method of manufacturing same and method of designing same
    6.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 有权
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US07303950B2

    公开(公告)日：2007-12-04

    申请号：US11034938

    申请日：2005-01-14

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor device including high frequency circuit with inductor
    8.
    发明授权
    Semiconductor device including high frequency circuit with inductor 有权
    半导体器件包括带电感的高频电路

    公开(公告)号：US06541841B2

    公开(公告)日：2003-04-01

    申请号：US10163613

    申请日：2002-06-07

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2900

    CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film is comprised of a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

    摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜由具有第一宽度的第一部分和大致垂直于埋入氧化膜的表面的方向延伸的第一部分和具有小于第一宽度的第二宽度的第二部分构成，并且连续地形成在第一 部分，大致垂直于掩埋氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

    Semiconductor device including high-frequency circuit with inductor
    9.
    发明授权
    Semiconductor device including high-frequency circuit with inductor 有权
    半导体器件包括具有电感的高频电路

    公开(公告)号：US06426543B1

    公开(公告)日：2002-07-30

    申请号：US09717038

    申请日：2000-11-22

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2900

    CPC分类号： H01L23/645 ,  H01L21/84 ,  H01L23/522 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/1203 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device with a spiral inductor is provided, which determines the area of an insulation layer to be provided in the surface of a wiring board thereunder. A trench isolation oxide film, which is a complete isolation oxide film including in part the structure of a partial isolation oxide film, is provided in a larger area of the surface of an SOI layer than that corresponding to the area of a spiral inductor. The trench isolation oxide film includes a first portion having a first width and extending in a direction approximately perpendicular the surface of a buried oxide film, and a second portion having a second width smaller than the first width and being continuously formed under the first portion, extending approximately perpendicular to the surface of the buried oxide film. The trench isolation oxide film is provided such that a horizontal distance between each end surface of the second portion and a corresponding end surface of the spiral inductor makes a predetermined distance or more.

    摘要翻译： 提供具有螺旋电感器的半导体器件，其确定要在其下面的布线板的表面中提供的绝缘层的面积。 在SOI层表面的与螺旋形电感器的面积相对应的面的大面积上，设置有作为部分隔离氧化膜的结构的完全隔离氧化膜的沟槽隔离氧化膜。 沟槽隔离氧化膜包括具有第一宽度并且在大致垂直于掩埋氧化膜的表面的方向上延伸的第一部分和具有小于第一宽度的第二宽度的第二部分并且连续地形成在第一部分下方， 大致垂直于埋入氧化膜的表面延伸。 沟槽隔离氧化膜被设置为使得第二部分的每个端表面与螺旋电感器的相应端面之间的水平距离达到预定距离或更大。

    Semiconductor device including upper, lower and side oxidation-resistant films
    10.
    发明授权
    Semiconductor device including upper, lower and side oxidation-resistant films 失效
    半导体器件包括上，下和侧抗氧化膜

    公开(公告)号：US6124619A

    公开(公告)日：2000-09-26

    申请号：US877202

    申请日：1997-06-17

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/4232

    摘要： In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36) respectively. Therefore, it is possible to inhibit portions in the vicinity of edge portions of the polysilicon layer (35) from being oxidized by an oxidant following oxidation for forming a gate insulating film (14). Thus, the polysilicon layer (35) is inhibited from deformation following oxidation, whereby the distance between an FS electrode (5) and a gate electrode (6) is sufficiently ensured. Consequently, isolation between the FS electrode (5) and the gate electrode (6) is improved.

    摘要翻译： 为了改善FS（场屏蔽）电极和栅电极（6）之间的隔离，形成FS电极（5）的主要部分的多晶硅层（35）的上主表面和下主表面被氮化物膜（ SiN膜）（34,36）。 因此，可以抑制多晶硅层（35）的边缘部分附近的部分被形成栅极绝缘膜（14）的氧化后的氧化剂氧化。 因此，抑制氧化后的多晶硅层（35）变形，从而充分确保了FS电极（5）与栅电极（6）之间的距离。 因此，提高了FS电极（5）与栅电极（6）之间的隔离。