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    Semiconductor device, method of manufacturing same and method of designing same
    2.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 失效
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US06953979B1

    公开(公告)日：2005-10-11

    申请号：US09466934

    申请日：1999-12-20

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor device, method of manufacturing same and method of designing same
    4.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 有权
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US07303950B2

    公开(公告)日：2007-12-04

    申请号：US11034938

    申请日：2005-01-14

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    Semiconductor device including upper, lower and side oxidation-resistant films
    5.
    发明授权
    Semiconductor device including upper, lower and side oxidation-resistant films 失效
    半导体器件包括上，下和侧抗氧化膜

    公开(公告)号：US6124619A

    公开(公告)日：2000-09-26

    申请号：US877202

    申请日：1997-06-17

    申请人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    发明人： Shigenobu Maeda ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L29/402 ,  H01L21/765 ,  H01L29/4232

    摘要： In order to improve isolation between an FS (field shielding) electrode and a gate electrode (6), upper and lower major surfaces of a polysilicon layer (35) forming a principal part of an FS electrode (5) are covered with nitride films (SiN films) (34, 36) respectively. Therefore, it is possible to inhibit portions in the vicinity of edge portions of the polysilicon layer (35) from being oxidized by an oxidant following oxidation for forming a gate insulating film (14). Thus, the polysilicon layer (35) is inhibited from deformation following oxidation, whereby the distance between an FS electrode (5) and a gate electrode (6) is sufficiently ensured. Consequently, isolation between the FS electrode (5) and the gate electrode (6) is improved.

    摘要翻译： 为了改善FS（场屏蔽）电极和栅电极（6）之间的隔离，形成FS电极（5）的主要部分的多晶硅层（35）的上主表面和下主表面被氮化物膜（ SiN膜）（34,36）。 因此，可以抑制多晶硅层（35）的边缘部分附近的部分被形成栅极绝缘膜（14）的氧化后的氧化剂氧化。 因此，抑制氧化后的多晶硅层（35）变形，从而充分确保了FS电极（5）与栅电极（6）之间的距离。 因此，提高了FS电极（5）与栅电极（6）之间的隔离。

    Semiconductor device, method of manufacturing same and method of designing same
    6.
    发明授权
    Semiconductor device, method of manufacturing same and method of designing same 有权
    半导体装置及其制造方法及其设计方法

    公开(公告)号：US07741679B2

    公开(公告)日：2010-06-22

    申请号：US11866693

    申请日：2007-10-03

    申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L23/62

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

    SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME AND METHOD OF DESIGNING SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME AND METHOD OF DESIGNING SAME 有权
    半导体器件，其制造方法和设计方法

    公开(公告)号：US20080315313A1

    公开(公告)日：2008-12-25

    申请号：US11866693

    申请日：2007-10-03

    申请人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    发明人： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

    摘要翻译： 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。