公开(公告)号：US4984216A

公开(公告)日：1991-01-08

申请号：US307701

申请日：1989-02-08

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C7/1045

摘要： A signal externally supplied to determine the operation mode is supplied to a first buffer circuit. A CAS signal is supplied to a second buffer circuit. The signals whose levels are converted by the first and second buffer circuits are supplied to a mode selection circuit. The operation of the mode selection circuit is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits. An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit. The address buffer circuit selects one of the received address signals based on the RAS signal anad the mode selection signal output from the mode selection circuit. A selected one of the address signals is supplied to a word line selection/driving circuit. When a mode other than the auto-refresh mode is specified, the mode setting signal is set up before the RAS signal is activated. The set-up allowance time with respect to the activation timing of the RAS signal is set to be larger than the minimum value of the set-up allowance time of the external address signal. The mode setting signal is latched by the mode selection circuit when the RAS signal is activated. The latched signal is used to select and control the operation mode.

公开(公告)号：US5051954A

公开(公告)日：1991-09-24

申请号：US406420

申请日：1989-09-11

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/10

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4096

摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

公开(公告)号：US5084635A

公开(公告)日：1992-01-28

申请号：US588809

申请日：1990-09-27

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： H03K19/20 ,  G06F15/78 ,  G06F17/50 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C7/1075 ,  G11C7/1015

摘要： A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.

公开(公告)号：US5007028A

公开(公告)日：1991-04-09

申请号：US552851

申请日：1990-07-16

申请人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

发明人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/1075

摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

公开(公告)号：US5233564A

公开(公告)日：1993-08-03

申请号：US712701

申请日：1991-06-10

申请人： Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C7/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46

CPC分类号： G11C29/46 ,  G11C29/003 ,  G11C29/02 ,  G11C7/1075

摘要： The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

公开(公告)号：US5239509A

公开(公告)日：1993-08-24

申请号：US824356

申请日：1992-01-23

申请人： Tatsuo Ikawa ,  Shigeo Ohshima

发明人： Tatsuo Ikawa ,  Shigeo Ohshima

IPC分类号： B23F5/02 ,  B23F23/00 ,  B23F23/12 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/14 ,  G11C29/20 ,  G11C29/56

CPC分类号： G11C29/20 ,  G11C29/02 ,  G11C7/1075

摘要： A semiconductor memory device having: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array; a mode switching unit for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit.

摘要翻译： 一种半导体存储器件，具有：用于随机访问存储单元阵列的RAM端口，所述存储单元阵列具有以矩阵形式布置的存储单元; 用于串行访问存储单元阵列的一行的数据的SAM端口; 模式切换单元，用于在外部接收模式切换信号时，将SAM端口的操作模式切换到普通数据输出模式和测试模式之间; 以及地址指针输出单元，用于当通过模式切换单元将操作模式切换到测试模式时，输出SAM端口的地址指针。

公开(公告)号：US5452255A

公开(公告)日：1995-09-19

申请号：US245438

申请日：1994-05-18

申请人： Naoyuki Mine ,  Tatsuo Ikawa

发明人： Naoyuki Mine ,  Tatsuo Ikawa

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/1075

摘要： There is provided a semiconductor memory device having output ports for serially accessing memory cells connected to a plurality of select lines, comprising: a decode counter adapted to be supplied with an initial value to count up to generate a plurality of counter address signals to output first decode signals obtained by decoding the counter address signals; and a serial decoder adapted to be supplied with the first decode signals respectively outputted from the decode counter to decode them to output second decode signals for selectig any one of the select lines.

摘要翻译： 提供一种半导体存储器件，其具有用于串行访问连接到多条选择线的存储器单元的输出端口，包括：解码计数器，其被配置为提供初始值进行计数以产生多个计数器地址信号以便先输出 解码通过解码计数器地址信号而得到的信号; 以及串行解码器，其被配置为被提供有从解码计数器分别输出的第一解码信号以对它们进行解码，以输出用于选择任意一个选择线的第二解码信号。

公开(公告)号：US5264727A

公开(公告)日：1993-11-23

申请号：US905417

申请日：1992-06-29

申请人： Masao Kudou ,  Tatsuo Ikawa

发明人： Masao Kudou ,  Tatsuo Ikawa

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L23/48

CPC分类号： G11C5/14 ,  H01L27/0218 ,  H01L2224/05554 ,  H01L2224/48091

摘要： There is disclosed a semiconductor integrated circuit device comprising: at least two first power supply voltage leads provided outside a chip adapted to be supplied with a first power supply voltage, e.g., VSS and a second power supply voltage, e.g., VCC and supplied with said first power supply voltage; at least two first power supply voltage terminals provided inside the chip, and connected to respective different ones of the first power supply voltage leads; an external input circuit adapted so that a signal is inputted from the outside of the chip, and connected to at least any one of first power supply voltage terminals; and an internal circuit adapted so that the signal is inputted from the external input circuit, and connected to one which is not connected to the external input circuit of the first power supply voltage terminals. Further, this semiconductor integrated circuit device may further comprise at least two second power supply voltage terminals provided inside the chip, and connected to respective different ones of the second power supply leads.

摘要翻译： 公开了一种半导体集成电路器件，包括：提供在芯片之外的至少两个第一电源电压引线，其适于被提供有第一电源电压，例如VSS和第二电源电压，例如VCC并且被提供有所述 第一电源电压; 至少两个第一电源电压端子，设置在芯片内部，并且连接到各个不同的第一电源电压引线; 外部输入电路，其适于使得信号从所述芯片的外部输入，并且连接到所述第一电源电压端子中的至少一个; 以及内部电路，其适于使得信号从外部输入电路输入，并且连接到未连接到第一电源电压端子的外部输入电路的电路。 此外，该半导体集成电路器件还可以包括设置在芯片内部的至少两个第二电源电压端子，并连接到各个不同的第二电源引线。

公开(公告)号：US4907200A

公开(公告)日：1990-03-06

申请号：US264246

申请日：1988-10-27

申请人： Tatsuo Ikawa ,  Katsushi Nagaba

发明人： Tatsuo Ikawa ,  Katsushi Nagaba

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/4085

摘要： A dynamic memory having pairs of bit lines. A sense amplifier is connected between each pair of bit lines for detecting data from the potential difference between these bit lines. The memory further comprises first and second pair of dummy word lines. A capacitor is coupled between the first of each pair of bit lines, on the one hand, and the first pair of dummy word lines, on the other. Similarly, a capacitor is coupled between the second of each pair of bit lines, on the one hand, and the second pair of dummy word lines, on the other. A first dummy word line driver is connected to the first pair of dummy word lines, for generating a reference potential in the first of each pair of bit lines. A second dummy word line driver is connected to the second pair of dummy word lines, for generating a reference potential in the second of each pair of bit lines. The memory also has a selection circuit for selecting either the first or second dummy word line driver. During a precharging period, either dummy word line driver sets both pairs of dummy word lines at a precharging potential. During a data-reading period, the dummy word line driver selected by the selection circuit sets the dummy word lines at a high potential and a low potential, respectively, and the dummy word line driver selected by the selection circuit sets both dummy word lines at a precharging potential.

摘要翻译： 具有位线对的动态存储器。 读取放大器连接在每对位线之间，用于从这些位线之间的电位差检测数据。 存储器还包括第一和第二对伪字线。 一方面，电容器耦合在每对位线中的第一位和第一对虚拟字线之间。 类似地，电容器一方面耦合在每对位线中的第二位和第二对伪字线之间。 第一虚拟字线驱动器连接到第一对虚拟字线对，用于在每对位线中的第一对中产生参考电位。 第二虚拟字线驱动器连接到第二对伪字线对，用于在每对位线中的第二对中产生参考电位。 存储器还具有用于选择第一或第二虚拟字线驱动器的选择电路。 在预充电期间，虚拟字线驱动器将两对虚拟字线设置为预充电电位。 在数据读取期间，由选择电路选择的虚拟字线驱动器将虚拟字线分别设定为高电位和低电位，由选择电路选择的虚拟字线驱动器将两个虚拟字线设为 预充电潜力。

公开(公告)号：US5377157A

公开(公告)日：1994-12-27

申请号：US121513

申请日：1993-09-16

申请人： Naoki Matsumoto ,  Tatsuo Ikawa ,  Shigeo Oshima

发明人： Naoki Matsumoto ,  Tatsuo Ikawa ,  Shigeo Oshima

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C7/1075

摘要： A multiport memory comprises a pair of memory cells, at least a pair of bit line and a pair of word lines on a random access port side. One of the memory cell is connected to one bit line and one word line and the other memory cell is connected to the other bit line and the other word line. A pair of data lines which are respectively connected to load elements are also provided in the random access port side of the multiport memory. A first switch circuit is connected between the pair of bit lines and the pair of data lines. On a serial access port side, a data register is connected between the pair of bit lines to receive data transmitted through the pair of bit lines. A second switch circuit for transmitting data is connected between the pair of bit lines and the data register. A control circuit opens the first switch circuit, before closing the second switch circuit to transmit data stored in the memory cells to the data register.

摘要翻译： 多端口存储器包括一对存储器单元，在随机存取端口侧至少一对位线和一对字线。 一个存储单元连接到一个位线和一个字线，另一个存储单元连接到另一个位线和另一个字线。 分别连接到负载元件的一对数据线也设置在多端口存储器的随机存取端口侧。 第一开关电路连接在该对位线和该对数据线之间。 在串行访问端口侧，数据寄存器连接在该对位线之间，以接收通过该位线对发送的数据。 用于发送数据的第二开关电路连接在该对位线和数据寄存器之间。 控制电路在闭合第二开关电路之前打开第一开关电路，以将存储在存储单元中的数据传送到数据寄存器。