公开(公告)号：US5051954A

公开(公告)日：1991-09-24

申请号：US406420

申请日：1989-09-11

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4097 ,  H01L27/10

CPC分类号： G11C11/4097 ,  G11C11/408 ,  G11C11/4096

摘要： Memory cells disposed in a matrix are divided into a plurality of blocks. Each block is constructed of n (n is a positive integer larger than 2) memory cell columns. One block is selected by one column address. One memory cell column in the n memory cell columns in a selected block is selected by a first gate. One memory cell column in the n memory cell colunns in a selected block is selected by a second gate. One memory cell in a selected memory cell column is selected by a row address. The data in a selected memory cell are stored in a register and output therefrom.

公开(公告)号：US4984216A

公开(公告)日：1991-01-08

申请号：US307701

申请日：1989-02-08

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/406 ,  G11C11/4076

CPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C7/1045

摘要： A signal externally supplied to determine the operation mode is supplied to a first buffer circuit. A CAS signal is supplied to a second buffer circuit. The signals whose levels are converted by the first and second buffer circuits are supplied to a mode selection circuit. The operation of the mode selection circuit is controlled by a RAS signal, and it latches and outputs a mode selection signal based on the outputs of the first and second buffer circuits. An externally supplied address signal and an address signal formed in the device are supplied to address buffer circuit. The address buffer circuit selects one of the received address signals based on the RAS signal anad the mode selection signal output from the mode selection circuit. A selected one of the address signals is supplied to a word line selection/driving circuit. When a mode other than the auto-refresh mode is specified, the mode setting signal is set up before the RAS signal is activated. The set-up allowance time with respect to the activation timing of the RAS signal is set to be larger than the minimum value of the set-up allowance time of the external address signal. The mode setting signal is latched by the mode selection circuit when the RAS signal is activated. The latched signal is used to select and control the operation mode.

公开(公告)号：US5239509A

公开(公告)日：1993-08-24

申请号：US824356

申请日：1992-01-23

申请人： Tatsuo Ikawa ,  Shigeo Ohshima

发明人： Tatsuo Ikawa ,  Shigeo Ohshima

IPC分类号： B23F5/02 ,  B23F23/00 ,  B23F23/12 ,  G11C7/10 ,  G11C11/401 ,  G11C11/41 ,  G11C29/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/14 ,  G11C29/20 ,  G11C29/56

CPC分类号： G11C29/20 ,  G11C29/02 ,  G11C7/1075

摘要： A semiconductor memory device having: a RAM port for randomly accessing a memory cell array having memory cells disposed in matrix; a SAM port for serially accessing data of one row of the memory cell array; a mode switching unit for switching the operation mode of the SAM port between an ordinary data output mode and a test mode, upon externally receiving a mode switching signal; and an address pointer outputting unit for outputting an address pointer of the SAM port when the operation mode is switched to the test mode by the mode switching unit.

摘要翻译： 一种半导体存储器件，具有：用于随机访问存储单元阵列的RAM端口，所述存储单元阵列具有以矩阵形式布置的存储单元; 用于串行访问存储单元阵列的一行的数据的SAM端口; 模式切换单元，用于在外部接收模式切换信号时，将SAM端口的操作模式切换到普通数据输出模式和测试模式之间; 以及地址指针输出单元，用于当通过模式切换单元将操作模式切换到测试模式时，输出SAM端口的地址指针。

公开(公告)号：US5084635A

公开(公告)日：1992-01-28

申请号：US588809

申请日：1990-09-27

申请人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Haruki Toda ,  Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： H03K19/20 ,  G06F15/78 ,  G06F17/50 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C7/1075 ,  G11C7/1015

摘要： A function selection circuit includes a first signal generating circuit for generating a plurality of first signals corresponding to each of all combinations of a plurality of input signal states; and a second signal generating circuit for selecting a plurality of logical sums of combinations of the plurality of first signals and generating a second signal corresponding to each of the plurality of logical sums which selectively activates an operation function indicated by a truth table.

公开(公告)号：US5007028A

公开(公告)日：1991-04-09

申请号：US552851

申请日：1990-07-16

申请人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

发明人： Shigeo Ohshima ,  Haruki Toda ,  Tatsuo Ikawa

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407

CPC分类号： G11C7/1075

摘要： This invention provides a multiport memory including a storage section A having bit lines BL and BL, a word line WL, a data transfer gate .phi.DT, and a dynamic memory cell Cs, and a serial port B having a serial access function in a column direction of the storage section, wherein the memory includes a circuit for disabling a word line signal WL for selecting one word line under the conditions that a row address strobe signal RAS is raised in a transfer cycle in which data held by the memory cell is transferred to the serial port, and that the data transfer to the serial port is completed by the data transfer gate .phi.DT.

公开(公告)号：US5233564A

公开(公告)日：1993-08-03

申请号：US712701

申请日：1991-06-10

申请人： Shigeo Ohshima ,  Tatsuo Ikawa

发明人： Shigeo Ohshima ,  Tatsuo Ikawa

IPC分类号： G11C7/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/46

CPC分类号： G11C29/46 ,  G11C29/003 ,  G11C29/02 ,  G11C7/1075

摘要： The disclosed semiconductor memory comprises a random access memory port, a serial access memory port, a data transfer gate formed between the two ports, and in particular a test signal generating circuit for generating a test signal to the data transfer gate to close the gate so that data stored in the serial access memory port can be read to outside, without transferring data from the random access memory port to the serial access memory port. Therefore, it is possible to discriminate an erroneous operation caused when data are read from the serial access memory port from that caused when data are transferred from the random access memory port to the serial access memory port.

公开(公告)号：US07986557B2

公开(公告)日：2011-07-26

申请号：US12533529

申请日：2009-07-31

申请人： Naoya Tokiwa ,  Shigeo Ohshima

发明人： Naoya Tokiwa ,  Shigeo Ohshima

IPC分类号： G11C16/04 ,  G11C5/14

CPC分类号： G11C16/30 ,  G11C5/143 ,  G11C5/145 ,  G11C8/06 ,  G11C8/10 ,  G11C16/0483

摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

摘要翻译： 存储器可以包括字线; 位线 对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

公开(公告)号：US06768691B2

公开(公告)日：2004-07-27

申请号：US10241908

申请日：2002-09-12

申请人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

发明人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

IPC分类号： G11C700

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066

摘要： A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.

摘要翻译： 一种半导体集成电路，包括：第一输出驱动部，其与参考时钟信号同步地输出数据信号; 第二输出驱动部，其输出规定所述数据信号的定时的数据选通信号; 以及分别控制所述第一和第二输出驱动部的驱动能力的驱动控制部。

公开(公告)号：US06483772B2

公开(公告)日：2002-11-19

申请号：US09951230

申请日：2001-09-12

申请人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

发明人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

IPC分类号： G11C800

CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1078

摘要： A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.

公开(公告)号：US06426915B2

公开(公告)日：2002-07-30

申请号：US09749008

申请日：2000-12-27

申请人： Shigeo Ohshima ,  Nobuo Watanabe

发明人： Shigeo Ohshima ,  Nobuo Watanabe

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/409

摘要： A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.

摘要翻译： 行访问命令和列访问命令在两个连续的时钟周期中作为一个分组提供给FCRAM，以便缩短随机访问时间和随机周期时间。 此时，通过使用第一命令来进行读/写操作的定义，并且响应于第一命令获取存储单元阵列的解码地址。 当响应于第一命令获取存储单元阵列的解码地址时，常规SDR / DDR-SDRAM的命令控制引脚用作地址引脚。