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    Nonvolatile semiconductor memory having page mode programming function
    2.
    发明授权
    Nonvolatile semiconductor memory having page mode programming function 失效
    具有页模式编程功能的非易失性半导体存储器

    公开(公告)号：US4943962A

    公开(公告)日：1990-07-24

    申请号：US263752

    申请日：1988-10-28

    申请人： Keniti Imamiya ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Shinji Saito

    发明人： Keniti Imamiya ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Shinji Saito

    IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/10

    CPC分类号： G11C16/10 ,  G11C2216/14

    摘要： A nonvolatile semiconductor memory of this invention is constituted to latch input data into data latch circuits and at the same time control the programming operation of the bit line load transistors when the chip enable signal is made active and a page programming power source voltage is set at the programming voltage, while the output enable signal is kept inactive. Further, when the output enable signal is made active or the programming power source voltage is set at a voltage different from the programming voltage, the data latch circuits are reset. The data latch circuits can be selectively specified by a preset combination of bits.

    摘要翻译： 本发明的非易失性半导体存储器被构造成将输入数据锁存到数据锁存电路中，同时在芯片使能信号有效时控制位线负载晶体管的编程操作，并将页面编程电源电压设置为 编程电压，而输出使能信号保持不活动。 此外，当使输出使能信号有效或者将编程电源电压设置为与编程电压不同的电压时，复位数据锁存电路。 数据锁存电路可以通过预设的位组合来选择性地指定。

    High voltage switching circuit in a nonvolatile memory
    4.
    发明授权
    High voltage switching circuit in a nonvolatile memory 失效
    非易失性存储器中的高压开关电路

    公开(公告)号：US4893275A

    公开(公告)日：1990-01-09

    申请号：US173563

    申请日：1988-03-25

    申请人： Sumio Tanaka ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Keniti Imamiya

    发明人： Sumio Tanaka ,  Shigeru Atsumi ,  Nobuaki Ohtsuka ,  Keniti Imamiya

    IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792 ,  H03K17/693

    CPC分类号： G11C16/12

    摘要： A nonvolatile semiconductor memory device includes a power voltage select circuit that is comprised of first and second power source nodes, an output node, first and second depletion type MOS transistors connected in series between the first power source node and the output node, a third MOS transistor connected between an interconnection point between the first and second depletion type MOS transistors and the second power source node, and a fourth MOS transistor connected between the second power source node and the output node.

    摘要翻译： 非易失性半导体存储器件包括由第一和第二电源节点组成的电源电压选择电路，串联连接在第一电源节点和输出节点之间的输出节点，第一和第二耗尽型MOS晶体管，第三MOS 连接在第一和第二耗尽型MOS晶体管与第二电源节点之间的互连点之间的晶体管，以及连接在第二电源节点和输出节点之间的第四MOS晶体管。

    Semiconductor nonvolatile memory device for controlling the potentials on bit lines
    5.
    发明授权
    Semiconductor nonvolatile memory device for controlling the potentials on bit lines 失效
    用于控制位线上的电位的半导体非易失性存储器件

    公开(公告)号：US5229963A

    公开(公告)日：1993-07-20

    申请号：US740665

    申请日：1991-08-02

    申请人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

    发明人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

    IPC分类号： G11C16/24

    CPC分类号： G11C16/24

    摘要： A nonvolatile semiconductor memory device comprising a power source terminal and a P-channel MOS transistor. A low power-source voltage is applied to the terminal during a read period. The source of the P-channel MOS transistor is coupled to the power source terminal. The conduction of the MOS transistor is controlled by data-writing operation. The drain of the MOS transistor is connected by a node to a plurality of bit lines. The device further comprises a plurality of memory cells and a plurality of N-channel MOS transistor. The memory cells have double-gate structure, each having a source coupled to the ground and a drain coupled to the corresponding bit line. Each N-channel MOS transistor has a source and a drain connected to the ground and the corresponding bit line, respectively, for discharging the bit line. Each N-channel MOS transistor is rendered conductive temporarily when the supply of the high power source voltage to the power source terminal is started, whereby the potential of the corresponding bit line is decreased. The bit-line potential is decreased sufficiently since the P-channel MOS transistors have a conductance greater than that of any other transistor incorporated in the device.

    摘要翻译： 一种非易失性半导体存储器件，包括电源端子和P沟道MOS晶体管。 在读取期间，向终端施加低电源电压。 P沟道MOS晶体管的源极耦合到电源端子。 通过数据写入操作来控制MOS晶体管的导通。 MOS晶体管的漏极由节点连接到多个位线。 该器件还包括多个存储单元和多个N沟道MOS晶体管。 存储单元具有双栅极结构，每个具有耦合到地的源极和耦合到相应位线的漏极。 每个N沟道MOS晶体管的源极和漏极分别连接到地和对应的位线，用于对位线进行放电。 当向电源端子供给高电源电压时，每个N沟道MOS晶体管暂时导通，从而相应位线的电位降低。 因为P沟道MOS晶体管的电导率大于装在器件中的任何其他晶体管的电导率，所以位线电位被充分降低。

    Cell array pattern layout for EEPROM device
    6.
    发明授权
    Cell array pattern layout for EEPROM device 失效
    CELL ARRAY PATTERN LAYOUT FOR EEPROM DEVICE

    公开(公告)号：US5105385A

    公开(公告)日：1992-04-14

    申请号：US703704

    申请日：1991-05-21

    申请人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

    发明人： Nobuaki Ohtsuka ,  Sumio Tanaka ,  Junichi Miyamoto ,  Shigeru Atsumi

    IPC分类号： H01L21/8247 ,  G11C7/14 ,  G11C16/28 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C7/14 ,  G11C16/28

    摘要： A memory cell array includes data storing memory cells which are arranged in a matrix form of m rows.times.n columns. The data storing memory cells are selected by means of m word lines and n bit lines. Dummy capacitance cells are arranged on the (n+1)th column of the memory cell array, and are connected to the word lines. The dummy capacitance cells are each formed of a transistor which has the same construction as a field transistor having a gate electrode formed of a polysilicon layer or the data storing memory cell and whose source is set in the electrically floating condition. Array edge memory cells are arranged on the (m+1)th row of the memory cell array, and are connected to n bit lines. The array edge memory cells have no influence on the circuit operation. A dummy memory cell is arranged in an intersecting position of the (m+1)th row and the (n+1)th column. A dummy bit line is connected to the dummy capacitance cells and dummy memory cell, and a dummy word line is connected to the array edge memory cell and dummy memory cell.

    Address detector of a redundancy memory cell
    7.
    发明授权
    Address detector of a redundancy memory cell 失效
    冗余存储单元的地址检测器

    公开(公告)号：US5233566A

    公开(公告)日：1993-08-03

    申请号：US614140

    申请日：1990-11-16

    申请人： Keniti Imamiya ,  Shigeru Atsumi ,  Sumio Tanaka

    发明人： Keniti Imamiya ,  Shigeru Atsumi ,  Sumio Tanaka

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/82 ,  H01L27/10

    CPC分类号： G11C29/789 ,  G11C29/24

    摘要： An address detector of a redundancy memory cell is provided including a programming element for storing address data for replacing a defective cell with the redundancy cell. In a test mode, the redundancy cell may be written to regardless of whether or not a memory cell is defective. Thus, the redundancy cell may be tested without programming a programming element that replaces a defective cell with a redundancy cell. The detector further includes a latch for latching the state of the programming element, and a data setting element for setting the latch in a test mode.

    摘要翻译： 提供冗余存储单元的地址检测器，其包括用于存储用于用冗余单元替换有缺陷单元的地址数据的编程元件。 在测试模式中，冗余单元可被写入，而不管存储单元是否有缺陷。 因此，可以对冗余单元进行测试，而不需要用冗余单元代替缺陷单元的编程元件。 检测器还包括用于锁存编程元件的状态的锁存器和用于在测试模式下设置锁存器的数据设置元件。

    Nonvolatile semiconductor memory device with a lightly-doped drain structure
    8.
    发明授权
    Nonvolatile semiconductor memory device with a lightly-doped drain structure 失效
    具有轻掺杂漏极结构的非易失性半导体存储器件

    公开(公告)号：US4788663A

    公开(公告)日：1988-11-29

    申请号：US42877

    申请日：1987-04-24

    申请人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

    发明人： Sumio Tanaka ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

    IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C7/00 ,  H01L29/78

    CPC分类号： G11C16/0441

    摘要： Each memory cell in an EPROM includes two memory cell transistors which share a common floating gate and have two separated drains, one of which is connected to a read bit line and the other of which is connected to write bit line. In this EPROM, the read memory cell transistor of the read bit line has a lower hot electron injection rate than the hot electron injection rate of the write memory cell transistor of the write bit line. A bit line voltage booster is connected to the read bit line.

    摘要翻译： EPROM中的每个存储单元包括两个存储单元晶体管，共享一个公共浮动栅极并具有两个分离的漏极，其中一个连接到读取位线，另一个连接到写入位线。 在该EPROM中，读取位线的读取存储单元晶体管的热电子注入速率低于写入位线的写入存储单元晶体管的热电子注入速率。 位线电压升压器连接到读位线。

    Nonvolatile semiconductor memory
    10.
    发明授权
    Nonvolatile semiconductor memory 失效
    非易失性半导体存储器

    公开(公告)号：US4825271A

    公开(公告)日：1989-04-25

    申请号：US50316

    申请日：1987-05-15

    申请人： Sumio Tanaka ,  Masaki Sato ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

    发明人： Sumio Tanaka ,  Masaki Sato ,  Shinji Saito ,  Shigeru Atsumi ,  Nobuaki Ohtsuka

    IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L27/20 ,  H01L29/34

    CPC分类号： H01L27/115 ,  Y10S257/915

    摘要： Disclosed is a nonvolatile semiconductor memory having a high access speed and high reliability. The memory includes a source diffusion region extending in one direction, a pair of first word lines arranged in parallel with the source diffusion region, such that the source diffusion region is interposed therebetween, drain diffusion regions disposed to face the source diffusion region, with the first word lines interposed therebetween, bit lines electrically connected to the drain diffusion regions and arranged to cross the first word lines, a channel region formed below each of the first word lines and positioned between the source diffusion region and the drain diffusion region, a floating gate electrode formed in an electrically floating manner above the channel region and below one of the pair of the first word lines, and a second word line formed above the source region and positioned between and electrically connected to the pair of first word lines.

    摘要翻译： 公开了具有高访问速度和高可靠性的非易失性半导体存储器。 存储器包括沿一个方向延伸的源极扩散区域，与源极扩散区域平行布置的一对第一字线，使得源极扩散区域介于其间，设置成面对源极扩散区域的漏极扩散区域， 插入其间的第一字线，与漏极扩散区域电连接且布置成跨越第一字线的位线，形成在每个第一字线下方并位于源极扩散区域和漏极扩散区域之间的沟道区域，浮置 栅极电极以电浮置方式形成在沟道区域上方并且位于该对第一字线中的一个之上，以及第二字线，形成在源极区域之上并且位于第一字线对之间并电连接到该第一字线对之间。