公开(公告)号：US20130341686A1

公开(公告)日：2013-12-26

申请号：US13533749

申请日：2012-06-26

Applicant: Ching-Kun Huang ,  Shih-Che Lin ,  Hung-Chih Yu

Inventor： Ching-Kun Huang ,  Shih-Che Lin ,  Hung-Chih Yu

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

公开(公告)号：US07421019B2

公开(公告)日：2008-09-02

申请号：US10871129

申请日：2004-06-18

Applicant: Chien-Hsing Liao ,  Wei-Min Chang ,  Tai-Kuo Woo ,  Shih-Che Lin ,  Jyh-Horng Wen

Inventor： Chien-Hsing Liao ,  Wei-Min Chang ,  Tai-Kuo Woo ,  Shih-Che Lin ,  Jyh-Horng Wen

IPC: H03H7/30

CPC classification number: H04L25/03038 ,  H03H21/0043 ,  H03H2021/0049 ,  H03H2021/0076 ,  H04L25/03057 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03617 ,  H04L2025/0363

Abstract: A hierarchical adaptive equalizer and a design method thereof are disclosed. The design method divides N delay elements into a plurality of adaptive algorithms, each of the adaptive algorithms having β delay elements. The design method logically structures a hierarchical tree with the adaptive algorithms. The hierarchical tree comprises α levels. A top first level of the hierarchical tree comprises βα−1 adaptive algorithms. A top second level of the hierarchical tree comprises βα−2 adaptive algorithms. A bottom level of the hierarchical tree comprises an adaptive algorithm.

Abstract translation: 公开了分级自适应均衡器及其设计方法。 设计方法将N个延迟元素分为多个自适应算法，每个自适应算法具有β延迟元素。 该设计方法通过自适应算法逻辑地构建了一个分层树。 分层树包含alpha级别。 分级树的顶级第一级包括β-α-1自适应算法。 层次树的顶级第二级包括β-α2-2自适应算法。 层次树的底层包括自适应算法。

公开(公告)号：US08883583B2

公开(公告)日：2014-11-11

申请号：US13533749

申请日：2012-06-26

Applicant: Ching-Kun Huang ,  Shih-Che Lin ,  Hung-Chih Yu

Inventor： Ching-Kun Huang ,  Shih-Che Lin ,  Hung-Chih Yu

IPC: H01L21/336

CPC classification number: H01L27/088 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/78

Abstract: Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers.

Abstract translation: 公开了半导体器件，晶体管及其制造方法。 在一个实施例中，半导体器件包括设置在工件上方的栅极电介质，设置在栅极电介质上方的栅极和设置在栅极和栅极电介质的侧壁上的间隔物。 源极区域设置在栅极的第一侧附近的间隔物处，并且漏极区域设置在栅极的第二侧上靠近隔离物的位置。 金属层设置在源极区域和漏极区域上。 金属层在间隔物下方延伸约25％或更大于间隔物的宽度。

公开(公告)号：US20050281327A1

公开(公告)日：2005-12-22

申请号：US10871129

申请日：2004-06-18

Applicant: Chien-Hsing Liao ,  Wei-Min Chang ,  Tai-Kuo Woo ,  Shih-Che Lin ,  Jyh-Horng Wen

Inventor： Chien-Hsing Liao ,  Wei-Min Chang ,  Tai-Kuo Woo ,  Shih-Che Lin ,  Jyh-Horng Wen

IPC: H03H21/00 ,  H03K5/159 ,  H04L25/03

CPC classification number: H04L25/03038 ,  H03H21/0043 ,  H03H2021/0049 ,  H03H2021/0076 ,  H04L25/03057 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03617 ,  H04L2025/0363

Abstract: A hierarchical adaptive equalizer and a design method thereof are disclosed. The design method divides N delay elements into a plurality of adaptive algorithms, each of the adaptive algorithms having β delay elements. The design method logically structures a hierarchical tree with the adaptive algorithms. The hierarchical tree comprises a levels. A top first level of the hierarchical tree comprises βα−1 adaptive algorithms. A top second level of the hierarchical tree comprises βα−2 adaptive algorithms. A bottom level of the hierarchical tree comprises an adaptive algorithm.

Abstract translation: 公开了分级自适应均衡器及其设计方法。 设计方法将N个延迟元素分为多个自适应算法，每个自适应算法具有β延迟元素。 该设计方法通过自适应算法逻辑地构建了一个分层树。 层次树包括一个层次。 分级树的顶级第一级包括β-α-1自适应算法。 层次树的顶级第二级包括β-α2-2自适应算法。 层次树的底层包括自适应算法。

公开(公告)号：US06718495B2

公开(公告)日：2004-04-06

申请号：US09975942

申请日：2001-10-15

Applicant: Shih-Che Lin

Inventor： Shih-Che Lin

IPC: G01R3128

CPC classification number: G01R31/31813 ,  G01R31/2891

Abstract: A CGROM testing device including a main body, a probe module and a circuit module. In the main body are disposed an EPROM having inbuilt character pattern data of a number of predetermined characters, a first IC having functions of data comparison and data memorization and a second IC having functions of signal output and control. The probe module receives the output signals of the CGROM of a controlling IC of a PCB. An analog multiplex selection circuit of the circuit module selects data and an analog-to-digital converting circuit converts the signals into digital signals. The first IC compares the character pattern data of predetermined characters inbuilt in the EPROM with the character code driven by the CGROM and the second IC outputs the comparison result.

Abstract translation: 一种CGROM测试装置，包括主体，探针模块和电路模块。 在主体中设置具有多个预定字符的内置字符图形数据的EPROM，具有数据比较和数据存储功能的第一IC和具有信号输出和控制功能的第二IC。 探头模块接收PCB的控制IC的CGROM的输出信号。 电路模块的模拟多路复用选择电路选择数据，模数转换电路将信号转换为数字信号。 第一IC将EPROM中构成的预定字符的字符图形数据与由CGROM驱动的字符代码进行比较，而第二IC输出比较结果。