公开(公告)号：US06680237B2

公开(公告)日：2004-01-20

申请号：US09967709

申请日：2001-09-27

申请人： Shih-Lung Chen ,  Hsiao-Lei Wang ,  Hwei-Lin Chuang ,  Yueh-Chuan Lee

发明人： Shih-Lung Chen ,  Hsiao-Lei Wang ,  Hwei-Lin Chuang ,  Yueh-Chuan Lee

IPC分类号： H01L2120

CPC分类号： H01L27/10867

摘要： A method of manufacturing a deep trench capacitor. A deep trench is formed in a substrate. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed, completely filling the deep trench. The first conductive layer has a seam. The first conductive layer is etched to open up the seam. A collar oxide layer is formed over the interior surface of the deep trench. A collar liner layer is formed over the collar oxide layer inside the deep trench. Using the collar liner layer as a mask, the collar oxide material above the first conductive layer and within the seam is removed. The collar liner layer is removed. Finally, a second conductive layer and a third conductive layer are sequentially formed inside the deep trench.

摘要翻译： 一种制造深沟槽电容器的方法。 在衬底中形成深沟槽。 依次形成保形电容器电介质层和第一导电层，完全填充深沟槽。 第一导电层具有接缝。 蚀刻第一导电层以打开接缝。 在深沟槽的内表面上形成环状氧化物层。 在深沟槽内部的轴环氧化物层上方形成轴环衬层。 使用套环内层作为掩模，去除第一导电层上方和接缝内的环氧化物材料。 衣领衬里层被去除。 最后，在深沟槽内依次形成第二导电层和第三导电层。

公开(公告)号：US06821842B1

公开(公告)日：2004-11-23

申请号：US10708227

申请日：2004-02-18

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10873 ,  H01L29/66181 ,  H01L29/945

摘要： A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

摘要翻译： 提供了一种动态随机存取存储器（DRAM）结构及其制造方法。 在制造过程中，在与隔离结构相邻的部分中，沟道区域形成有与衬底相同的导电性的掺杂区域。 通过在形成沟槽之后但在有源区的定义之前，通过在邻近沟道区的电容器沟槽的上部通过进行倾斜注入而将离子注入到衬底中来形成掺杂区。

公开(公告)号：US20050062089A1

公开(公告)日：2005-03-24

申请号：US10711623

申请日：2004-09-29

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10873 ,  H01L29/66181 ,  H01L29/945

摘要： A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

摘要翻译： 提供了一种动态随机存取存储器（DRAM）结构及其制造方法。 在制造过程中，在与隔离结构相邻的部分中，沟道区域形成有与衬底相同的导电性的掺杂区域。 通过在形成沟槽之后但在有源区的定义之前，通过在邻近沟道区的电容器沟槽的上部通过进行倾斜注入而将离子注入到衬底中来形成掺杂区。

公开(公告)号：US07009238B2

公开(公告)日：2006-03-07

申请号：US10967181

申请日：2004-10-19

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L29/76

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/923

摘要： A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

摘要翻译： 一种制造沟槽电容器的方法，包括提供半导体衬底，在衬底中形成深沟槽，在沟槽的表面上形成薄的牺牲层，以及在薄牺牲层上形成半球状硅晶粒层，其中牺牲层 层的厚度在随后的步骤中用作蚀刻停止以去除半球状硅晶粒层的至少一部分，并且是导电的。

公开(公告)号：US06987044B2

公开(公告)日：2006-01-17

申请号：US10669346

申请日：2003-09-25

申请人： Shih-Lung Chen ,  Yueh-Chuan Lee

发明人： Shih-Lung Chen ,  Yueh-Chuan Lee

IPC分类号： H01L27/148 ,  H01L29/768

CPC分类号： H01L27/10867

摘要： A method for forming a volatile memory structure. A buried trench capacitor in each of a pair of neighboring trenches formed in a substrate. An asymmetric collar insulating layer is formed over an upper portion of the sidewall of each trench and has a high and a low level portions. A conductive layer is formed overlying the buried trench capacitor and below the surface of the substrate. The high level portion is adjacent to the substrate between the neighboring trenches and the low level portion is covered by the conductive layer. A dielectric layer is formed overlying the conductive layer. Two access transistors are formed on the substrate outside of the pair of the neighboring trenches, respectively, which have source/drain regions electrically connecting to the conductive layer. A volatile memory structure is also disclosed.

摘要翻译： 一种用于形成易失性存储器结构的方法。 在一对相邻的沟槽中的每一个中形成在衬底中的埋沟槽电容器。 在每个沟槽的侧壁的上部上形成不对称的环形绝缘层，并且具有高和低的电平部分。 形成覆盖在埋入沟槽电容器上并在衬底表面下方的导电层。 高电平部分与相邻沟槽之间的衬底相邻，并且低电平部分被导电层覆盖。 形成覆盖导电层的电介质层。 两个存取晶体管分别形成在一对相邻沟槽之外的衬底的外侧，其中源/漏区电连接到导电层。 还公开了易失性存储器结构。

公开(公告)号：US06953961B2

公开(公告)日：2005-10-11

申请号：US10711623

申请日：2004-09-29

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10873 ,  H01L29/66181 ,  H01L29/945

摘要： A dynamic random access memory (DRAM) structure and a fabricating process thereof are provided. In the fabricating process, a channel region is formed with a doped region having identical conductivity as the substrate in a section adjacent to an isolation structure. The doped region is formed in a self-aligned process by conducting a tilt implantation implanting ions into the substrate through the upper portion of the capacitor trench adjacent to the channel region after forming the trench but before the definition of the active region.

摘要翻译： 提供了一种动态随机存取存储器（DRAM）结构及其制造方法。 在制造过程中，在与隔离结构相邻的部分中，沟道区域形成有与衬底相同的导电性的掺杂区域。 通过在形成沟槽之后但在有源区的定义之前，通过在邻近沟道区的电容器沟槽的上部通过进行倾斜注入而将离子注入到衬底中来形成掺杂区。

公开(公告)号：US20050067646A1

公开(公告)日：2005-03-31

申请号：US10669346

申请日：2003-09-25

申请人： Shih-Lung Chen ,  Yueh-Chuan Lee

发明人： Shih-Lung Chen ,  Yueh-Chuan Lee

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10867

摘要： A method for forming a volatile memory structure. A buried trench capacitor in each of a pair of neighboring trenches formed in a substrate. An asymmetric collar insulating layer is formed over an upper portion of the sidewall of each trench and has a high and a low level portions. A conductive layer is formed overlying the buried trench capacitor and below the surface of the substrate. The high level portion is adjacent to the substrate between the neighboring trenches and the low level portion is covered by the conductive layer. A dielectric layer is formed overlying the conductive layer. Two access transistors are formed on the substrate outside of the pair of the neighboring trenches, respectively, which have source/drain regions electrically connecting to the conductive layer. A volatile memory structure is also disclosed.

摘要翻译： 一种用于形成易失性存储器结构的方法。 在一对相邻的沟槽中的每一个中形成在衬底中的埋沟槽电容器。 在每个沟槽的侧壁的上部上形成不对称的环形绝缘层，并且具有高和低的电平部分。 形成覆盖在埋入沟槽电容器上并在衬底表面下方的导电层。 高电平部分与相邻沟槽之间的衬底相邻，并且低电平部分被导电层覆盖。 形成覆盖导电层的电介质层。 两个存取晶体管分别形成在一对相邻沟槽之外的衬底的外侧，其中源/漏区电连接到导电层。 还公开了易失性存储器结构。

公开(公告)号：US06849529B2

公开(公告)日：2005-02-01

申请号：US10327043

申请日：2002-12-24

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/38

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/923

摘要： A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

公开(公告)号：US20050079681A1

公开(公告)日：2005-04-14

申请号：US10967181

申请日：2004-10-19

申请人： Yueh-Chuan Lee ,  Shih-Lung Chen

发明人： Yueh-Chuan Lee ,  Shih-Lung Chen

IPC分类号： H01L21/334 ,  H01L21/8242 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L27/1087 ,  H01L29/66181 ,  H01L29/945 ,  Y10S438/923

摘要： A method for manufacturing a trench capacitor that includes providing a semiconductor substrate, forming a deep trench in the substrate, forming a thin sacrificial layer on a surface of the trench, and forming a hemispherical silicon grain layer over the thin sacrificial layer, wherein the sacrificial layer has a thickness to act as an etch stop during a subsequent step to remove at least a portion of the hemispherical silicon grain layer, and is electrically conductive.

摘要翻译： 一种制造沟槽电容器的方法，包括提供半导体衬底，在衬底中形成深沟槽，在沟槽的表面上形成薄的牺牲层，以及在薄牺牲层上形成半球状硅晶粒层，其中牺牲层 层的厚度在随后的步骤中用作蚀刻停止以去除半球状硅晶粒层的至少一部分，并且是导电的。

公开(公告)号：US20060128157A1

公开(公告)日：2006-06-15

申请号：US11338679

申请日：2006-01-25

申请人： Yueh-Chuan Lee ,  Ming-Sheng Tung

发明人： Yueh-Chuan Lee ,  Ming-Sheng Tung

IPC分类号： H01L21/311 ,  H01L21/461 ,  H01L21/302

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114 ,  H01L21/823425 ,  H01L21/823456 ,  H01L29/42376

摘要： A semiconductor structure with partially etched gate and method of fabricating the same. A semiconductor structure with a single-sided or dual-sided partially etched gate comprises a gate dielectric layer, a gate conductive layer and a cap layer sequentially stacked on a substrate to form a gate structure, and a lining layer disposed on sidewalls of the gate structure, wherein the lining layer is partially etched to expose the adjacent gate structure. In addition, an inter-layer dielectric layer covers the gate structure and a contact is formed in the inter-layer dielectric layer, exposing the substrate and a portion of the gate structure therein, wherein the lining layer of the exposed portion of the gate structure is partially removed.

摘要翻译： 具有部分蚀刻栅极的半导体结构及其制造方法。 具有单面或双面部分蚀刻栅极的半导体结构包括依次层叠在衬底上以形成栅极结构的栅介质层，栅极导电层和覆盖层，以及设置在栅极侧壁上的衬层 结构，其中衬里层被部分蚀刻以暴露相邻的栅极结构。 此外，层间电介质层覆盖栅极结构，并且在层间电介质层中形成接触，将衬底和栅极结构的一部分暴露于其中，其中栅极结构的暴露部分的衬层 被部分删除。